PPCLK_PHYCLK
dcn3_init_single_clock(clk_mgr, PPCLK_PHYCLK,
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));
clk_select = PPCLK_PHYCLK;
ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
PPCLK_PHYCLK)) == 0,
clk_select = PPCLK_PHYCLK;
ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
if (!driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete)
CLK_MAP(PHYCLK, PPCLK_PHYCLK),
if (!table_member[PPCLK_PHYCLK].SnapToDiscrete)
CLK_MAP(PHYCLK, PPCLK_PHYCLK),