PPCLK_DISPCLK
dcn3_init_single_clock(clk_mgr, PPCLK_DISPCLK,
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
dcn32_init_single_clock(clk_mgr, PPCLK_DISPCLK,
clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK,
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK,
if (clk == PPCLK_DISPCLK)
block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DISPCLK;
return dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DISPCLK) ?
return dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DISPCLK) ?
dcn401_init_single_clock(clk_mgr, PPCLK_DISPCLK,
clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);
case PPCLK_DISPCLK:
clk_select = PPCLK_DISPCLK;
ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
PPCLK_DISPCLK)) == 0,
clk_select = PPCLK_DISPCLK;
ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
if (!driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete)
CLK_MAP(DISPCLK, PPCLK_DISPCLK),
if (!table_member[PPCLK_DISPCLK].SnapToDiscrete)
CLK_MAP(DISPCLK, PPCLK_DISPCLK),