PPCLK_DCFCLK
dcn32_init_single_clock(clk_mgr, PPCLK_DCFCLK,
clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
if (clk == PPCLK_DCFCLK)
case PPCLK_DCFCLK:
dcn401_init_single_clock(clk_mgr, PPCLK_DCFCLK,
clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {
block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DCFCLK;
if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {
case PPCLK_DCFCLK:
CLK_MAP(DCEFCLK, PPCLK_DCFCLK),
*value = metrics->CurrClock[PPCLK_DCFCLK];
case PPCLK_DCFCLK:
CLK_MAP(DCEFCLK, PPCLK_DCFCLK),
*value = metrics->CurrClock[PPCLK_DCFCLK];
CLK_MAP(DCEFCLK, PPCLK_DCFCLK),
*value = metrics->CurrClock[PPCLK_DCFCLK];
case PPCLK_DCFCLK: