PPC
{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}},
{"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
{"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
{"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
{"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
{"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
{"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
{"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
{"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
{"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},
{"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},
{"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}},
{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}},
{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}},
{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}},
{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}},
{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
{"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
{"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},
{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
{"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
{"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
{"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}},
{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}},
{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}},
{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}},
{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}},
{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}},
{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}},
{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
{"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},
{"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
{"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
{"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
{"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
{"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
{"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
{"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}},
{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
{"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
{"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}},
{"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}},
{"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
{"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},
{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
{"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
{"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
{"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
{"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
{"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
{"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
{"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
{"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
{"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
{"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
{"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
{"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
{"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
{"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
{"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
{"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
{"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
{"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
{"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
{"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
{"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
{"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
{"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
{"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
{"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
case PPC: