drivers/powercap/intel_rapl_common.c

1066

rapl_write_pl_data(rd, POWER_LIMIT1, PL_CLAMP, mode);

drivers/powercap/intel_rapl_common.c

112

[POWER_LIMIT1] = "long_term",

drivers/powercap/intel_rapl_common.c

128

if (pl < POWER_LIMIT1 || pl > POWER_LIMIT4)

drivers/powercap/intel_rapl_common.c

136

if (pl == POWER_LIMIT1)

drivers/powercap/intel_rapl_common.c

1487

for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) {

drivers/powercap/intel_rapl_common.c

160

case POWER_LIMIT1:

drivers/powercap/intel_rapl_common.c

166

return POWER_LIMIT1;

drivers/powercap/intel_rapl_common.c

2133

for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) {

drivers/powercap/intel_rapl_common.c

2284

for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) {

drivers/powercap/intel_rapl_common.c

2305

for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++)

drivers/powercap/intel_rapl_common.c

349

ret = rapl_write_pl_data(rd, POWER_LIMIT1, PL_ENABLE, mode);

drivers/powercap/intel_rapl_common.c

353

ret = rapl_read_pl_data(rd, POWER_LIMIT1, PL_ENABLE, false, &val);

drivers/powercap/intel_rapl_common.c

378

if (rd->rpl[POWER_LIMIT1].locked) {

drivers/powercap/intel_rapl_common.c

383

ret = rapl_read_pl_data(rd, POWER_LIMIT1, PL_ENABLE, true, &val);

drivers/powercap/intel_rapl_common.c

444

for (i = POWER_LIMIT1, j = 0; i < NR_POWER_LIMITS; i++) {

drivers/powercap/intel_rapl_common.c

615

rp->priv->limits[i] |= BIT(POWER_LIMIT1);

drivers/powercap/intel_rapl_common.c

617

for (t = POWER_LIMIT1; t < NR_POWER_LIMITS; t++) {

drivers/powercap/intel_rapl_common.c

662

[POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,

drivers/powercap/intel_rapl_common.c

718

[POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, TPMI_POWER_LIMIT_MASK, 0,

drivers/powercap/intel_rapl_common.c

803

case POWER_LIMIT1:

drivers/powercap/intel_rapl_tpmi.c

225

trp->priv.limits[domain_type] |= BIT(POWER_LIMIT1);