POSR_PLL2_LOCK
CCU_PLL_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR3, MPMU_POSR, POSR_PLL2_LOCK,
MPMU_POSR, POSR_PLL2_LOCK, CLK_SET_RATE_GATE);