drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

221

REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

289

*sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

350

REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

353

value = REG_READ(AUX_SW_STATUS);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

379

AUX_SW_STATUS,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

105

AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

106

AUX_SF(AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

129

AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

130

AUX_SF(AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

41

SRI(AUX_SW_STATUS, DP_AUX, id)

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

49

SRI(AUX_SW_STATUS, DP_AUX, id), \

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

60

uint32_t AUX_SW_STATUS;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

574

SRI_ARR(AUX_SW_STATUS, DP_AUX, id)

drivers/gpu/drm/radeon/radeon_dp_auxch.c

153

tmp = RREG32(AUX_SW_STATUS + aux_offset[instance]);