drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

242

value = REG_UPDATE_4(AUX_SW_DATA,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

246

AUX_SW_DATA, COMPOSE_AUX_SW_DATA_16_20(request->action, request->address));

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

248

value = REG_SET_2(AUX_SW_DATA, value,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

250

AUX_SW_DATA, COMPOSE_AUX_SW_DATA_8_15(request->address));

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

252

value = REG_SET(AUX_SW_DATA, value,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

253

AUX_SW_DATA, COMPOSE_AUX_SW_DATA_0_7(request->address));

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

256

value = REG_SET(AUX_SW_DATA, value,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

257

AUX_SW_DATA, request->length - 1);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

269

value = REG_SET(AUX_SW_DATA, value,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

270

AUX_SW_DATA, request->data[i]);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

300

REG_UPDATE_SEQ_3(AUX_SW_DATA,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

305

REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

323

REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

101

AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

102

AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

103

AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

104

AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

125

AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

126

AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

127

AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

128

AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

153

AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

179

AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

205

AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

37

SRI(AUX_SW_DATA, DP_AUX, id), \

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

46

SRI(AUX_SW_DATA, DP_AUX, id), \

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

56

uint32_t AUX_SW_DATA;

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

78

type AUX_SW_DATA;\

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

571

SRI_ARR(AUX_SW_DATA, DP_AUX, id), SRI_ARR(AUX_SW_CONTROL, DP_AUX, id), \

drivers/gpu/drm/radeon/radeon_dp_auxch.c

121

WREG32(AUX_SW_DATA + aux_offset[instance],

drivers/gpu/drm/radeon/radeon_dp_auxch.c

125

WREG32(AUX_SW_DATA + aux_offset[instance],

drivers/gpu/drm/radeon/radeon_dp_auxch.c

129

WREG32(AUX_SW_DATA + aux_offset[instance],

drivers/gpu/drm/radeon/radeon_dp_auxch.c

133

WREG32(AUX_SW_DATA + aux_offset[instance],

drivers/gpu/drm/radeon/radeon_dp_auxch.c

139

WREG32(AUX_SW_DATA + aux_offset[instance],

drivers/gpu/drm/radeon/radeon_dp_auxch.c

178

WREG32(AUX_SW_DATA + aux_offset[instance],

drivers/gpu/drm/radeon/radeon_dp_auxch.c

181

tmp = RREG32(AUX_SW_DATA + aux_offset[instance]);

drivers/gpu/drm/radeon/radeon_dp_auxch.c

185

tmp = RREG32(AUX_SW_DATA + aux_offset[instance]);