Symbol: AUX_SW_CONTROL
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
237
REG_UPDATE_2(AUX_SW_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
276
REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
100
AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
122
AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
123
AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
124
AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
38
SRI(AUX_SW_CONTROL, DP_AUX, id), \
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
47
SRI(AUX_SW_CONTROL, DP_AUX, id), \
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
57
uint32_t AUX_SW_CONTROL;
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
98
AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
99
AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
571
SRI_ARR(AUX_SW_DATA, DP_AUX, id), SRI_ARR(AUX_SW_CONTROL, DP_AUX, id), \
drivers/gpu/drm/radeon/radeon_dp_auxch.c
113
WREG32(AUX_SW_CONTROL + aux_offset[instance],
drivers/gpu/drm/radeon/radeon_dp_auxch.c
115
WREG32(AUX_SW_CONTROL + aux_offset[instance],
drivers/gpu/drm/radeon/radeon_dp_auxch.c
148
WREG32(AUX_SW_CONTROL + aux_offset[instance],