PORT_RWC_BITS
temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
writel(portsc & ~(PORT_RWC_BITS | PORT_RESET),
temp &= ~PORT_RWC_BITS;
~(PORT_RWC_BITS | PORT_RESUME),
temp & ~(PORT_RWC_BITS | PORT_RESET),
temp &= ~PORT_RWC_BITS;
temp &= ~PORT_RWC_BITS;
~PORT_RWC_BITS;
fotg210_writel(fotg210, PORT_RWC_BITS, status_reg);
pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
ehci_writel(ehci, PORT_RWC_BITS,
temp &= ~PORT_RWC_BITS;
status = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
temp = ehci_readl(ehci, sreg) & ~PORT_RWC_BITS;
u32 temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS;
u32 t1 = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
u32 t1 = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
temp &= ~(PORT_RWC_BITS | PORT_SUSPEND | PORT_RESUME);
port_status &= ~(PORT_PE | PORT_RWC_BITS);
status = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
port_status &= ~PORT_RWC_BITS;
status = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
temp &= ~PORT_RWC_BITS;
temp &= ~(PORT_RWC_BITS | PORT_SUSPEND | PORT_RESUME);
ehci_writel(ehci, temp & ~(PORT_RWC_BITS | PORT_RESET),
temp &= ~PORT_RWC_BITS;
writel(PORT_RWC_BITS, &oxu->regs->port_status[port]);
writel((temp & ~PORT_RWC_BITS) | PORT_PEC, status_reg);
temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
writel(temp & ~(PORT_RWC_BITS | PORT_POWER),
writel((temp & ~PORT_RWC_BITS) | PORT_CSC, status_reg);
writel((temp & ~PORT_RWC_BITS) | PORT_OCC, status_reg);
writel(temp & ~(PORT_RWC_BITS | PORT_RESUME),
writel(temp & ~(PORT_RWC_BITS | PORT_RESET),
temp &= ~PORT_RWC_BITS;
temp &= ~PORT_RWC_BITS;
u32 t1 = readl(reg) & ~PORT_RWC_BITS;
temp &= ~(PORT_RWC_BITS
temp &= ~(PORT_RWC_BITS | PORT_RESUME);
portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
val = readl_relaxed(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;