drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

4950

int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

4966

t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

6351

(is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

6448

PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

9215

PORT_REG(port, XGMAC_PORT_CFG_A) :

drivers/pinctrl/pinctrl-pic32.c

1827

return !!(readl(bank->reg_base + PORT_REG) & BIT(offset));

drivers/pinctrl/pinctrl-pic32.c

1837

writel(mask, bank->reg_base + PIC32_SET(PORT_REG));

drivers/pinctrl/pinctrl-pic32.c

1839

writel(mask, bank->reg_base + PIC32_CLR(PORT_REG));