PORT_REGS
reg = readl(PORT_REGS(port) + UTMI_PLL_CTRL_REG);
writel(reg, PORT_REGS(port) + UTMI_PLL_CTRL_REG);
reg = readl(PORT_REGS(port) + UTMI_CAL_CTRL_REG);
writel(reg, PORT_REGS(port) + UTMI_CAL_CTRL_REG);
reg = readl(PORT_REGS(port) + UTMI_TX_CH_CTRL_REG);
writel(reg, PORT_REGS(port) + UTMI_TX_CH_CTRL_REG);
reg = readl(PORT_REGS(port) + UTMI_RX_CH_CTRL0_REG);
writel(reg, PORT_REGS(port) + UTMI_RX_CH_CTRL0_REG);
reg = readl(PORT_REGS(port) + UTMI_RX_CH_CTRL1_REG);
writel(reg, PORT_REGS(port) + UTMI_RX_CH_CTRL1_REG);
reg = readl(PORT_REGS(port) + UTMI_CHGDTC_CTRL_REG);
writel(reg, PORT_REGS(port) + UTMI_CHGDTC_CTRL_REG);
reg = readl(PORT_REGS(port) + UTMI_DIG_CTRL1_REG);
writel(reg, PORT_REGS(port) + UTMI_DIG_CTRL1_REG);
reg = readl(PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
writel(reg, PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
reg = readl(PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
writel(reg, PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
ret = readl_poll_timeout(PORT_REGS(port) + UTMI_CAL_CTRL_REG, reg,
ret = readl_poll_timeout(PORT_REGS(port) + UTMI_CAL_CTRL_REG, reg,
ret = readl_poll_timeout(PORT_REGS(port) + UTMI_PLL_CTRL_REG, reg,