PORT_PLS_MASK
switch (portsc & PORT_PLS_MASK) {
temp &= ~PORT_PLS_MASK;
portsc = readl(&port_regs->portsc) & PORT_PLS_MASK;
#define CDNSP_PORT_RWS (PORT_PLS_MASK | PORT_WKCONN_E | PORT_WKDISC_E)
link_state = portsc & PORT_PLS_MASK;
if ((portsc & PORT_PLS_MASK) != XDEV_RXDETECT) {
portsc &= ~PORT_PLS_MASK;
link_state = portsc & PORT_PLS_MASK;
link_state = portsc & PORT_PLS_MASK;
if ((temp & PORT_PLS_MASK) != XDEV_U0) {
|| (temp & PORT_PLS_MASK) >= XDEV_U3) {
u32 pls = temp & PORT_PLS_MASK;
if ((temp & PORT_PLS_MASK) == XDEV_U3)
if ((temp & PORT_PLS_MASK) == XDEV_U3) {
(t1 & PORT_PLS_MASK) == XDEV_POLLING) {
if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
t2 &= ~PORT_PLS_MASK;
if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
switch (portsc & PORT_PLS_MASK) {
portsc &= ~PORT_PLS_MASK;
temp &= ~PORT_PLS_MASK;
u32 pls = status_reg & PORT_PLS_MASK;
bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
if ((portsc & PORT_PLS_MASK) != XDEV_U3)
if (vdev && (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
((portsc & PORT_PLS_MASK) == XDEV_U0 ||
(portsc & PORT_PLS_MASK) == XDEV_U1 ||
(portsc & PORT_PLS_MASK) == XDEV_U2)) {
if ((value & PORT_PLS_MASK) != XDEV_U3) {
if (((portsc & PORT_PLS_MASK) == XDEV_U3) || ((portsc & DEV_SPEED_MASK) == XDEV_FS))
if ((portsc & PORT_PLS_MASK) == XDEV_RESUME)
if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
(pm_val & PORT_PLS_MASK) == XDEV_U0,
(portsc & PORT_PLS_MASK) == XDEV_RESUME)
(portsc & PORT_PLS_MASK) == XDEV_RESUME)
switch (portsc & PORT_PLS_MASK) {