AUX_REG
maybe_emit_mod(&prog, AUX_REG, dst_reg, true);
EMIT3(0x0F, 0x44, add_2reg(0xC0, AUX_REG, dst_reg));
EMIT_mov(AUX_REG, src_reg);
src_reg = AUX_REG;
src_reg = AUX_REG;
[AUX_REG] = 3, /* R11 temp register */
EMIT_mov(AUX_REG, dst_reg);
dst_reg = AUX_REG;
EMIT_mov(insn->dst_reg, AUX_REG);
BIT(AUX_REG) |
EMIT_mov(AUX_REG, src_reg);
maybe_emit_1mod(&prog, AUX_REG, true);
EMIT2_off32(0x81, add_1reg(0xC0, AUX_REG), insn->off);
maybe_emit_mod(&prog, AUX_REG, BPF_REG_AX, true);
EMIT2(0x29, add_2reg(0xC0, AUX_REG, BPF_REG_AX));
maybe_emit_mod(&prog, AUX_REG, BPF_REG_AX, true);
EMIT2(0x39, add_2reg(0xC0, AUX_REG, BPF_REG_AX));
emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0);
maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64);
add_2reg(0xC0, AUX_REG, real_src_reg));
real_dst_reg, AUX_REG,
uint32_t addr = AUX_REG(AUX_CONTROL);
addr = AUX_REG(AUX_DPHY_RX_CONTROL0);
dm_read_reg(CTX, AUX_REG(reg_name))
AUX_REG(reg_name), \
dm_read_reg(CTX, AUX_REG(reg_name))
dm_write_reg(CTX, AUX_REG(reg_name), val)
dm_read_reg(CTX, AUX_REG(reg_name))
dm_write_reg(CTX, AUX_REG(reg_name), val)
dm_read_reg(CTX, AUX_REG(reg_name))
dm_write_reg(CTX, AUX_REG(reg_name), val)
dm_read_reg(CTX, AUX_REG(reg_name))
dm_write_reg(CTX, AUX_REG(reg_name), val)
dm_read_reg(CTX, AUX_REG(reg_name))
dm_write_reg(CTX, AUX_REG(reg_name), val)
dm_read_reg(CTX, AUX_REG(reg_name))
dm_write_reg(CTX, AUX_REG(reg_name), val)