PORT_D
if (port == PORT_D)
return port == PORT_B || port == PORT_C || port == PORT_D;
if (port == PORT_D)
[PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
bool ddi_d_present = intel_bios_is_port_present(display, PORT_D);
[PORT_D] = TRANSCODER_C,
if (port == PORT_D)
case PORT_D:
port_name(port - PORT_D_XELPD + PORT_D),
port == PORT_D)
dpd_is_edp = intel_dp_is_port_edp(display, PORT_D);
g4x_hdmi_init(display, PCH_HDMID, PORT_D);
g4x_dp_init(display, PCH_DP_D, PORT_D);
has_port = intel_bios_is_port_present(display, PORT_D);
g4x_dp_init(display, CHV_DP_D, PORT_D);
g4x_hdmi_init(display, CHV_HDMID, PORT_D);
g4x_dp_init(display, DP_D, PORT_D);
case PORT_D:
display_runtime->port_mask &= ~BIT(PORT_D);
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D),
PORT_TC1 = PORT_D,
case PORT_D:
case PORT_D:
case PORT_D:
if (port == PORT_D || port == PORT_E) {
case PORT_D:
case PORT_D:
case PORT_D:
case PORT_D:
assert_pch_hdmi_disabled(display, pipe, PORT_D, PCH_HDMID);
ibx_sanitize_pch_dp_port(display, PORT_D, PCH_DP_D);
ibx_sanitize_pch_hdmi_port(display, PORT_D, PCH_HDMID);
drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D);
assert_pch_dp_disabled(display, pipe, PORT_D, PCH_DP_D);
case PORT_D:
case PORT_D:
g4x_dp_port_enabled(display, PCH_DP_D, PORT_D, &panel_pipe);
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
~DPLL_CTRL2_DDI_CLK_OFF(PORT_D);
DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D);
DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);
(PORT_D << TRANS_DDI_PORT_SHIFT) |
vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
clean_virtual_dp_monitor(vgpu, PORT_D);
return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
port = PORT_D;
port = PORT_D;
port = PORT_D;
MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
if (port != PORT_B && port != PORT_D) {
ret = intel_gvt_set_edid(vgpu, PORT_D);
MMIO_D(PORT_CLK_SEL(PORT_D));
MMIO_D(DDI_BUF_CTL(PORT_D));
MMIO_D(DP_TP_CTL(PORT_D));
MMIO_D(DP_TP_STATUS(PORT_D));