drivers/gpu/drm/i915/display/g4x_hdmi.c

658

return port == PORT_B || port == PORT_C;

drivers/gpu/drm/i915/display/g4x_hdmi.c

660

return port == PORT_B || port == PORT_C || port == PORT_D;

drivers/gpu/drm/i915/display/icl_dsi.c

1116

if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))

drivers/gpu/drm/i915/display/icl_dsi.c

1544

if (intel_dsi->ports == BIT(PORT_B))

drivers/gpu/drm/i915/display/icl_dsi.c

1556

if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A)))

drivers/gpu/drm/i915/display/icl_dsi.c

1559

else if (intel_dsi->ports == BIT(PORT_B))

drivers/gpu/drm/i915/display/icl_dsi.c

1685

if (intel_dsi->ports == BIT(PORT_B))

drivers/gpu/drm/i915/display/icl_dsi.c

2008

intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);

drivers/gpu/drm/i915/display/icl_dsi.c

242

port = PORT_B;

drivers/gpu/drm/i915/display/intel_audio_regs.h

161

#define VLV_AUD_PORT_EN_DBG(port) _MMIO_BASE_PORT3(VLV_DISPLAY_BASE, (port) - PORT_B, \

drivers/gpu/drm/i915/display/intel_bios.c

1650

enum port port_bc = DISPLAY_VER(display) >= 11 ? PORT_B : PORT_C;

drivers/gpu/drm/i915/display/intel_bios.c

2345

[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },

drivers/gpu/drm/i915/display/intel_bios.c

2360

[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },

drivers/gpu/drm/i915/display/intel_bios.c

2371

[PORT_B] = { -1 },

drivers/gpu/drm/i915/display/intel_bios.c

2380

[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },

drivers/gpu/drm/i915/display/intel_bios.c

2420

return PORT_B;

drivers/gpu/drm/i915/display/intel_ddi.c

1938

case PORT_B:

drivers/gpu/drm/i915/display/intel_ddi.c

3395

[PORT_B] = TRANSCODER_A,

drivers/gpu/drm/i915/display/intel_ddi.c

5103

case PORT_B:

drivers/gpu/drm/i915/display/intel_display.c

7876

found = intel_sdvo_init(display, PCH_SDVOB, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7878

g4x_hdmi_init(display, PCH_HDMIB, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7880

g4x_dp_init(display, PCH_DP_B, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7915

has_edp = intel_dp_is_port_edp(display, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7916

has_port = intel_bios_is_port_present(display, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7918

has_edp &= g4x_dp_init(display, VLV_DP_B, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7920

g4x_hdmi_init(display, VLV_HDMIB, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7955

found = intel_sdvo_init(display, GEN3_SDVOB, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7959

g4x_hdmi_init(display, GEN4_HDMIB, PORT_B);

drivers/gpu/drm/i915/display/intel_display.c

7963

g4x_dp_init(display, DP_B, PORT_B);

drivers/gpu/drm/i915/display/intel_display.h

104

case PORT_B:

drivers/gpu/drm/i915/display/intel_display_debugfs.c

865

lpsp_capable = encoder->port <= PORT_B;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

872

lpsp_capable = encoder->port <= PORT_B;

drivers/gpu/drm/i915/display/intel_display_device.c

1036

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |

drivers/gpu/drm/i915/display/intel_display_device.c

1053

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |

drivers/gpu/drm/i915/display/intel_display_device.c

1076

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |

drivers/gpu/drm/i915/display/intel_display_device.c

1173

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |

drivers/gpu/drm/i915/display/intel_display_device.c

1238

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D_XELPD) |

drivers/gpu/drm/i915/display/intel_display_device.c

1341

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \

drivers/gpu/drm/i915/display/intel_display_device.c

1367

BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_TC1) | BIT(PORT_TC2),

drivers/gpu/drm/i915/display/intel_display_device.c

263

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */

drivers/gpu/drm/i915/display/intel_display_device.c

272

.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */

drivers/gpu/drm/i915/display/intel_display_device.c

282

.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */

drivers/gpu/drm/i915/display/intel_display_device.c

292

.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */

drivers/gpu/drm/i915/display/intel_display_device.c

307

.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */

drivers/gpu/drm/i915/display/intel_display_device.c

403

.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */

drivers/gpu/drm/i915/display/intel_display_device.c

415

.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */

drivers/gpu/drm/i915/display/intel_display_device.c

426

.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */

drivers/gpu/drm/i915/display/intel_display_device.c

438

.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */

drivers/gpu/drm/i915/display/intel_display_device.c

453

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */

drivers/gpu/drm/i915/display/intel_display_device.c

482

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */

drivers/gpu/drm/i915/display/intel_display_device.c

507

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */

drivers/gpu/drm/i915/display/intel_display_device.c

536

.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */

drivers/gpu/drm/i915/display/intel_display_device.c

585

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),

drivers/gpu/drm/i915/display/intel_display_device.c

638

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),

drivers/gpu/drm/i915/display/intel_display_device.c

657

.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */

drivers/gpu/drm/i915/display/intel_display_device.c

682

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),

drivers/gpu/drm/i915/display/intel_display_device.c

833

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)

drivers/gpu/drm/i915/display/intel_display_device.c

931

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),

drivers/gpu/drm/i915/display/intel_display_device.c

939

.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D),

drivers/gpu/drm/i915/display/intel_display_irq.c

1335

PORT_A : PORT_B;

drivers/gpu/drm/i915/display/intel_display_irq.c

1367

port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;

drivers/gpu/drm/i915/display/intel_display_irq.c

1760

port = PORT_B;

drivers/gpu/drm/i915/display/intel_display_power.c

2389

.port_end = PORT_B,

drivers/gpu/drm/i915/display/intel_display_regs.h

2036

#define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)

drivers/gpu/drm/i915/display/intel_dp.c

6943

port != PORT_B && port != PORT_C))

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1182

case PORT_B:

drivers/gpu/drm/i915/display/intel_dpio_phy.c

176

[DPIO_CH0] = { .port = PORT_B },

drivers/gpu/drm/i915/display/intel_dpio_phy.c

199

[DPIO_CH0] = { .port = PORT_B },

drivers/gpu/drm/i915/display/intel_dpio_phy.c

665

case PORT_B:

drivers/gpu/drm/i915/display/intel_dpio_phy.c

679

case PORT_B:

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

214

case PORT_B:

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

92

if (intel_dsi->ports & BIT(PORT_B))

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

93

return PORT_B;

drivers/gpu/drm/i915/display/intel_dvo.c

107

.port = PORT_B,

drivers/gpu/drm/i915/display/intel_hdcp.c

2285

case PORT_B ... PORT_F:

drivers/gpu/drm/i915/display/intel_hdcp.c

465

case PORT_B:

drivers/gpu/drm/i915/display/intel_hdmi.c

2744

case PORT_B:

drivers/gpu/drm/i915/display/intel_hdmi.c

2767

case PORT_B:

drivers/gpu/drm/i915/display/intel_hdmi.c

2787

case PORT_B:

drivers/gpu/drm/i915/display/intel_hdmi.c

2891

WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C);

drivers/gpu/drm/i915/display/intel_hdmi.c

2909

case PORT_B:

drivers/gpu/drm/i915/display/intel_lpe_audio.c

337

ppdata = &pdata->port[port - PORT_B];

drivers/gpu/drm/i915/display/intel_lpe_audio.c

364

pdata->notify_audio_lpe(display->audio.lpe.platdev, port - PORT_B);

drivers/gpu/drm/i915/display/intel_pch_display.c

100

assert_pch_hdmi_disabled(display, pipe, PORT_B, PCH_HDMIB);

drivers/gpu/drm/i915/display/intel_pch_display.c

169

ibx_sanitize_pch_dp_port(display, PORT_B, PCH_DP_B);

drivers/gpu/drm/i915/display/intel_pch_display.c

174

ibx_sanitize_pch_hdmi_port(display, PORT_B, PCH_HDMIB);

drivers/gpu/drm/i915/display/intel_pch_display.c

438

drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D);

drivers/gpu/drm/i915/display/intel_pch_display.c

85

assert_pch_dp_disabled(display, pipe, PORT_B, PCH_DP_B);

drivers/gpu/drm/i915/display/intel_pipe_crc.c

107

case PORT_B:

drivers/gpu/drm/i915/display/intel_psr.c

1232

return pipe <= PIPE_B && port <= PORT_B;

drivers/gpu/drm/i915/display/intel_sdvo.c

1627

if (intel_sdvo->base.port == PORT_B)

drivers/gpu/drm/i915/display/intel_sdvo.c

234

if (intel_sdvo->base.port == PORT_B)

drivers/gpu/drm/i915/display/intel_sdvo.c

2622

if (sdvo->base.port == PORT_B)

drivers/gpu/drm/i915/display/intel_sdvo.c

2645

if (sdvo->base.port == PORT_B)

drivers/gpu/drm/i915/display/intel_sdvo.c

2689

if (sdvo->base.port == PORT_B) {

drivers/gpu/drm/i915/display/intel_sdvo.c

2716

if (sdvo->base.port == PORT_B)

drivers/gpu/drm/i915/display/intel_sdvo.c

3368

return port == PORT_B;

drivers/gpu/drm/i915/display/intel_sdvo.c

3370

return port == PORT_B || port == PORT_C;

drivers/gpu/drm/i915/display/intel_sdvo.c

3466

if (intel_sdvo->base.port == PORT_B)

drivers/gpu/drm/i915/display/intel_sdvo.c

412

#define SDVO_NAME(svdo) ((svdo)->base.port == PORT_B ? "SDVOB" : "SDVOC")

drivers/gpu/drm/i915/gvt/display.c

310

if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {

drivers/gpu/drm/i915/gvt/display.c

317

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=

drivers/gpu/drm/i915/gvt/display.c

319

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=

drivers/gpu/drm/i915/gvt/display.c

322

vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=

drivers/gpu/drm/i915/gvt/display.c

326

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=

drivers/gpu/drm/i915/gvt/display.c

328

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=

drivers/gpu/drm/i915/gvt/display.c

333

(PORT_B << TRANS_DDI_PORT_SHIFT) |

drivers/gpu/drm/i915/gvt/display.c

364

(PORT_B << TRANS_DDI_PORT_SHIFT) |

drivers/gpu/drm/i915/gvt/display.c

418

if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {

drivers/gpu/drm/i915/gvt/display.c

420

~DPLL_CTRL2_DDI_CLK_OFF(PORT_B);

drivers/gpu/drm/i915/gvt/display.c

422

DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B);

drivers/gpu/drm/i915/gvt/display.c

424

DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);

drivers/gpu/drm/i915/gvt/display.c

431

(PORT_B << TRANS_DDI_PORT_SHIFT) |

drivers/gpu/drm/i915/gvt/display.c

434

vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=

drivers/gpu/drm/i915/gvt/display.c

436

vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=

drivers/gpu/drm/i915/gvt/display.c

439

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

440

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;

drivers/gpu/drm/i915/gvt/display.c

727

if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {

drivers/gpu/drm/i915/gvt/display.c

787

clean_virtual_dp_monitor(vgpu, PORT_B);

drivers/gpu/drm/i915/gvt/display.c

816

return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,

drivers/gpu/drm/i915/gvt/edid.c

110

port = PORT_B;

drivers/gpu/drm/i915/gvt/edid.c

128

port = PORT_B;

drivers/gpu/drm/i915/gvt/edid.c

94

port = PORT_B;

drivers/gpu/drm/i915/gvt/handlers.c

2377

MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2383

MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2389

MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2793

MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,

drivers/gpu/drm/i915/gvt/handlers.c

570

case PORT_B:

drivers/gpu/drm/i915/gvt/handlers.c

677

if (port != PORT_B && port != PORT_D) {

drivers/gpu/drm/i915/gvt/handlers.c

964

calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E))

drivers/gpu/drm/i915/gvt/mmio.c

284

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=

drivers/gpu/drm/i915/gvt/mmio.c

286

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=

drivers/gpu/drm/i915/gvt/vgpu.c

378

ret = intel_gvt_set_edid(vgpu, PORT_B);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1145

MMIO_D(BXT_PHY_CTL(PORT_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1148

MMIO_D(BXT_PORT_PLL_ENABLE(PORT_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

501

MMIO_D(PORT_CLK_SEL(PORT_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

532

MMIO_D(DDI_BUF_CTL(PORT_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

537

MMIO_D(DP_TP_CTL(PORT_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

542

MMIO_D(DP_TP_STATUS(PORT_B));

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

1013

ret = ipu7_isys_phy_config(isys, PORT_B, 2, aggregation);

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

1017

gpreg_write(isys, PORT_B, PHY_RESET, 1);

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

1018

gpreg_write(isys, PORT_B, PHY_SHUTDOWN, 1);

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

1019

dwc_csi_write(isys, PORT_B, DPHY_RSTZ, 1);

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

1020

dwc_csi_write(isys, PORT_B, PHY_SHUTDOWNZ, 1);

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

1021

dwc_csi_write(isys, PORT_B, CSI2_RESETN, 1);

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

1022

ret = ipu7_isys_phy_ready(isys, PORT_B);

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

1026

gpreg_write(isys, PORT_B, PHY_LANE_FORCE_CONTROL, 0);

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

1027

gpreg_write(isys, PORT_B, PHY_CLK_LANE_FORCE_CONTROL, 0);

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

1040

ipu7_isys_csi_phy_reset(isys, PORT_B);

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

512

id == PORT_B || id == PORT_C) {

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

554

if (!is_ipu7(isys->adev->isp->hw_ver) || id == PORT_B || id == PORT_C)

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

983

ipu7_isys_csi_phy_reset(isys, PORT_B);

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

984

gpreg_write(isys, PORT_B, PHY_CLK_LANE_CONTROL, 0x0);

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

985

gpreg_write(isys, PORT_B, PHY_LANE_CONTROL_EN, 0x3);

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

986

gpreg_write(isys, PORT_B, PHY_CLK_LANE_FORCE_CONTROL, 0x2);

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

987

gpreg_write(isys, PORT_B, PHY_LANE_FORCE_CONTROL, 0xf);

drivers/staging/media/ipu7/ipu7-isys-csi-phy.c

988

gpreg_write(isys, PORT_B, PHY_MODE, csi2->phy_mode);