Symbol: AUX_CONTROL
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
120
value = REG_READ(AUX_CONTROL);
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
122
AUX_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
129
AUX_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
137
AUX_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
141
REG_WRITE(AUX_CONTROL, value);
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
146
REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1,
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
152
AUX_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
155
REG_WRITE(AUX_CONTROL, value);
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
157
REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0,
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
116
AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
117
AUX_SF(AUX_CONTROL, AUX_RESET, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
118
AUX_SF(AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
35
SRI(AUX_CONTROL, DP_AUX, id), \
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
44
SRI(AUX_CONTROL, DP_AUX, id), \
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
54
uint32_t AUX_CONTROL;
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
94
AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
651
uint32_t addr = AUX_REG(AUX_CONTROL);
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
654
set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL);
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
655
set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN);
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
134
uint32_t AUX_CONTROL;
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
40
SRI(AUX_CONTROL, DP_AUX, id), \
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
1430
AUX_REG_UPDATE_2(AUX_CONTROL,
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
35
SRI(AUX_CONTROL, DP_AUX, id), \
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h
74
uint32_t AUX_CONTROL;
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
313
SRI_ARR(AUX_CONTROL, DP_AUX, id), SRI_ARR(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
570
SRI_ARR(AUX_CONTROL, DP_AUX, id), SRI_ARR(AUX_ARB_CONTROL, DP_AUX, id), \
drivers/gpu/drm/radeon/radeon_dp_auxch.c
104
tmp = RREG32(AUX_CONTROL + aux_offset[instance]);
drivers/gpu/drm/radeon/radeon_dp_auxch.c
110
WREG32(AUX_CONTROL + aux_offset[instance], tmp);