PORT
PORT(AU1000_UART0_PHYS_ADDR, AU1000_UART0_INT),
PORT(AU1000_UART1_PHYS_ADDR, AU1000_UART1_INT),
PORT(AU1000_UART2_PHYS_ADDR, AU1000_UART2_INT),
PORT(AU1000_UART3_PHYS_ADDR, AU1000_UART3_INT),
PORT(AU1000_UART0_PHYS_ADDR, AU1500_UART0_INT),
PORT(AU1000_UART3_PHYS_ADDR, AU1500_UART3_INT),
PORT(AU1000_UART0_PHYS_ADDR, AU1100_UART0_INT),
PORT(AU1000_UART1_PHYS_ADDR, AU1100_UART1_INT),
PORT(AU1000_UART3_PHYS_ADDR, AU1100_UART3_INT),
PORT(AU1000_UART0_PHYS_ADDR, AU1550_UART0_INT),
PORT(AU1000_UART1_PHYS_ADDR, AU1550_UART1_INT),
PORT(AU1000_UART3_PHYS_ADDR, AU1550_UART3_INT),
PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT),
PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT),
PORT(AU1300_UART0_PHYS_ADDR, AU1300_UART0_INT),
PORT(AU1300_UART1_PHYS_ADDR, AU1300_UART1_INT),
PORT(AU1300_UART2_PHYS_ADDR, AU1300_UART2_INT),
PORT(AU1300_UART3_PHYS_ADDR, AU1300_UART3_INT),
#ifndef PORT
return *((volatile IOTYPE *)PORT(offset)) & 0xFF;
*((volatile IOTYPE *)PORT(offset)) = value & 0xFF;
[MACH_LEMOTE_FL2E] = PORT(4, 1843200),
[MACH_LEMOTE_FL2F] = PORT(3, 1843200),
[MACH_LEMOTE_LL2F] = PORT(3, 1843200),
PORT(0x3f8, 4),
PORT(0x2f8, 3),
PORT(0x3f8, 4),
PORT(0x2f8, 3),
PORT(0x3f8, 0),
PORT(0x2f8, 3),
PORT(0x3f8, 0),
PORT(0x2f8, 3),
PORT(0x3e8, 4),
PORT(0x2e8, 3),
#define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & (1 << (19 + (12 * (PORT)))))
#define BU2614_PORT_MASK MKMASK(PORT)
FLOWC_PARAM(PORT, csk->tx_chan);
#define QLC_83XX_VXLAN_UDP_DPORT(PORT) ((PORT & 0xffff) << 16)
#define ENET_VLAN_TBL_SHIFT(PORT) ((PORT) * 4)
#define ZCP_RAM_SEL_CFIFO(PORT) (0x10 + (PORT))
#define RESET_CFIFO_RST(PORT) (0x1 << (PORT))
#define CFIFO_ECC(PORT) (FZC_ZCP + 0x000a0UL + (PORT) * 8UL)
#define TXC_PORT_CTL(PORT) (FZC_TXC + 0x20020UL + (PORT)*0x100UL)
#define TXC_PKT_STUFFED(PORT) (FZC_TXC + 0x20030UL + (PORT)*0x100UL)
#define TXC_PKT_XMIT(PORT) (FZC_TXC + 0x20038UL + (PORT)*0x100UL)
#define TXC_ROECC_CTL(PORT) (FZC_TXC + 0x20040UL + (PORT)*0x100UL)
#define TXC_ROECC_ST(PORT) (FZC_TXC + 0x20048UL + (PORT)*0x100UL)
#define TXC_RO_DATA0(PORT) (FZC_TXC + 0x20050UL + (PORT)*0x100UL)
#define TXC_RO_DATA1(PORT) (FZC_TXC + 0x20058UL + (PORT)*0x100UL)
#define TXC_RO_DATA2(PORT) (FZC_TXC + 0x20060UL + (PORT)*0x100UL)
#define TXC_RO_DATA3(PORT) (FZC_TXC + 0x20068UL + (PORT)*0x100UL)
#define TXC_RO_DATA4(PORT) (FZC_TXC + 0x20070UL + (PORT)*0x100UL)
#define TXC_SFECC_CTL(PORT) (FZC_TXC + 0x20078UL + (PORT)*0x100UL)
#define TXC_SFECC_ST(PORT) (FZC_TXC + 0x20080UL + (PORT)*0x100UL)
#define TXC_SF_DATA0(PORT) (FZC_TXC + 0x20088UL + (PORT)*0x100UL)
#define TXC_SF_DATA1(PORT) (FZC_TXC + 0x20090UL + (PORT)*0x100UL)
#define TXC_SF_DATA2(PORT) (FZC_TXC + 0x20098UL + (PORT)*0x100UL)
#define TXC_SF_DATA3(PORT) (FZC_TXC + 0x200a0UL + (PORT)*0x100UL)
#define TXC_SF_DATA4(PORT) (FZC_TXC + 0x200a8UL + (PORT)*0x100UL)
#define TXC_RO_TIDS(PORT) (FZC_TXC + 0x200b0UL + (PORT)*0x100UL)
#define TXC_RO_STATE0(PORT) (FZC_TXC + 0x200b8UL + (PORT)*0x100UL)
#define TXC_RO_STATE1(PORT) (FZC_TXC + 0x200c0UL + (PORT)*0x100UL)
#define TXC_RO_STATE2(PORT) (FZC_TXC + 0x200c8UL + (PORT)*0x100UL)
#define TXC_RO_STATE3(PORT) (FZC_TXC + 0x200d0UL + (PORT)*0x100UL)
#define TXC_RO_CTL(PORT) (FZC_TXC + 0x200d8UL + (PORT)*0x100UL)
#define TXC_RO_ST_DATA0(PORT) (FZC_TXC + 0x200e0UL + (PORT)*0x100UL)
#define TXC_RO_ST_DATA1(PORT) (FZC_TXC + 0x200e8UL + (PORT)*0x100UL)
#define TXC_RO_ST_DATA2(PORT) (FZC_TXC + 0x200f0UL + (PORT)*0x100UL)
#define TXC_RO_ST_DATA3(PORT) (FZC_TXC + 0x200f8UL + (PORT)*0x100UL)
#define TXC_PORT_PACKET_REQ(PORT) (FZC_TXC + 0x20100UL + (PORT)*0x100UL)
#define TXC_INT_STAT_VAL_SHIFT(PORT) ((PORT) * 8)
#define TXC_INT_STAT_VAL(PORT) (0x3f << TXC_INT_STAT_VAL_SHIFT(PORT))
#define TXC_INT_STAT_SF_CE(PORT) (0x01 << TXC_INT_STAT_VAL_SHIFT(PORT))
#define TXC_INT_STAT_SF_UE(PORT) (0x02 << TXC_INT_STAT_VAL_SHIFT(PORT))
#define TXC_INT_STAT_RO_CE(PORT) (0x04 << TXC_INT_STAT_VAL_SHIFT(PORT))
#define TXC_INT_STAT_RO_UE(PORT) (0x08 << TXC_INT_STAT_VAL_SHIFT(PORT))
#define TXC_INT_STAT_REORDER_ERR(PORT) (0x10 << TXC_INT_STAT_VAL_SHIFT(PORT))
#define TXC_INT_STAT_PKTASM_DEAD(PORT) (0x20 << TXC_INT_STAT_VAL_SHIFT(PORT))
#define TXC_INT_MASK_VAL_SHIFT(PORT) ((PORT) * 8)
#define TXC_INT_MASK_VAL(PORT) (0x3f << TXC_INT_STAT_VAL_SHIFT(PORT))
#define LDN_MAC(PORT) (64 + (PORT))
mode = TX_MODE_SEL(PORT, SYNC, REPLACE_TS) |
TX_MODE_SEL(PORT, DELAY_REQ, REPLACE_TS) |
TX_MODE_SEL(PORT, PDELAY_REQ, REPLACE_TS) |
TX_MODE_SEL(PORT, PDELAY_RESP, REPLACE_TS);
mode = RX_MODE_SEL(PORT, SYNC, INSERT_TS_64) |
RX_MODE_SEL(PORT, DELAY_REQ, INSERT_TS_64) |
RX_MODE_SEL(PORT, PDELAY_REQ, INSERT_TS_64) |
RX_MODE_SEL(PORT, PDELAY_RESP, INSERT_TS_64);
void __iomem *mem = info->membase[PORT(pin)];
void __iomem *mem = info->membase[PORT(pin)];
int port = PORT(offset);
int port = PORT(info->mfp[mfp].pin);
#define PCFG_PORT_MASK(PORT) \
(((1 << PCFG_PORT_BITWIDTH) - 1) << (PCFG_PORT_BITWIDTH * (PORT)))
#define DEFPINFUNCGRP(NAME, PORT, MODE, ISGPIO) { \
.port = (PORT), .mode = (MODE), \
int port = PORT(pin);
int port = PORT(pin);
int port = PORT(pin);
if (PORT(pin) == PORT3)
#define GPIO_BASE(p) (REG_OFF * PORT(p))
#define __PORT_DATA(pn, pfx, sfx) PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN)
#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
.name = __stringify(PORT##_pin), \
.enum_id = PORT##_pin##_DATA, \
PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
PORT##pfx##_OUT, PORT##pfx##_IN)
CPU_ALL_PORT(_PORT_ENTRY, PORT, unused), \
0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
PORT##nr##_FN0, PORT##nr##_FN1, \
PORT##nr##_FN2, PORT##nr##_FN3, \
PORT##nr##_FN4, PORT##nr##_FN5, \
PORT##nr##_FN6, PORT##nr##_FN7 \
#define SETPORT(PORT, VAL) outb( (VAL), (PORT) )
#define GETPORT(PORT) inb( PORT )
#define SETBITS(PORT, BITS) outb( (inb(PORT) | (BITS)), (PORT) )
#define CLRBITS(PORT, BITS) outb( (inb(PORT) & ~(BITS)), (PORT) )
#define TESTHI(PORT, BITS) ((inb(PORT) & (BITS)) == (BITS))
#define TESTLO(PORT, BITS) ((inb(PORT) & (BITS)) == 0)
BFA_TRC_FILE(FCS, PORT);
BFA_TRC_FILE(CNA, PORT);
#define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
#define UART_ZILOG(PORT) ((struct uart_ip22zilog_port *)(PORT))
#define IP22ZILOG_GET_CURR_REG(PORT, REGNUM) \
(UART_ZILOG(PORT)->curregs[REGNUM])
#define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL) \
((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))
#define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel __iomem *)((PORT)->membase))
#define UART_ZILOG(PORT) ((struct uart_sunzilog_port *)(PORT))
si_other.sin_port = htons(PORT);
run_assign_reuse(AF_INET, SOCK_STREAM, "127.0.0.1", PORT);
run_assign_reuse(AF_INET6, SOCK_STREAM, "::1", PORT);
run_assign_reuse(AF_INET, SOCK_DGRAM, "127.0.0.1", PORT);
run_assign_reuse(AF_INET6, SOCK_DGRAM, "::1", PORT);
.port = PORT,
if (peer.sin_port != htons(PORT))
die_port(&peer, PORT);
if (peer.sin_port != htons((PORT + 1)))
die_port(&peer, PORT + 1);
sa1.sin_port = htons(PORT);
sa2.sin_port = htons(PORT + 1);
fprintf(stderr, "Opening INADDR_ANY:%d\n", PORT);
fprintf(stderr, "Opening INADDR_ANY:%d after closing ipv6 socket\n", PORT);
.sin6_port = htons(PORT),
.sin_port = htons(PORT),
fprintf(stderr, "Opening 127.0.0.1:%d\n", PORT);
fprintf(stderr, "Opening INADDR_ANY:%d\n", PORT);
fprintf(stderr, "Opening in6addr_any:%d\n", PORT);
daddr4.sin_port = htons(PORT);
daddr6.sin6_port = htons(PORT);
static const int PORT = 8888;
addr4.sin_port = htons(PORT);
addr6.sin6_port = htons(PORT);
daddr4->sin_port = htons(PORT);
daddr6->sin6_port = htons(PORT);
static const int PORT = 8888;
addr4->sin_port = htons(PORT);
addr6->sin6_port = htons(PORT);
daddr4->sin_port = htons(PORT);
daddr6->sin6_port = htons(PORT);
static const int PORT = 8888;
addr4->sin_port = htons(PORT);
addr6->sin6_port = htons(PORT);
static const int PORT = 8888;
addr4->sin_port = htons(PORT);
addr6->sin6_port = htons(PORT);
daddr.sin_port = htons(PORT);
addr4.sin_port = htons(PORT);
addr6.sin6_port = htons(PORT);
daddr4.sin_port = htons(PORT);
daddr6.sin6_port = htons(PORT);
static const int PORT = 8891;