PLL_VCO_SAI
clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll("vco_in",
{ CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q",
{ NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,