PLL_OFF_TEST_CTL_U1
[PLL_OFF_TEST_CTL_U1] = 0x24,
[PLL_OFF_TEST_CTL_U1] = 0x2c,
[PLL_OFF_TEST_CTL_U1] = 0x24,
[PLL_OFF_TEST_CTL_U1] = 0x34,
[PLL_OFF_TEST_CTL_U1] = 0x34,
[PLL_OFF_TEST_CTL_U1] = 0x34,
[PLL_OFF_TEST_CTL_U1] = 0x2c,
#define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])