PLL_DIV2
[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
[5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
[1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
[9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
[13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 },
[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
[1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
[5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
{ CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
{ CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
[2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
[6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
[2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
[6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
[2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
[6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;
cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
int div = PLL_DIV2;
cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
int div = PLL_DIV2;
cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;