PMU1CRU_RESET_OFFSET
PMU1CRU_RESET_OFFSET(SRST_P_SPI2AHB, 0, 0),
PMU1CRU_RESET_OFFSET(SRST_H_SPI2AHB, 0, 1),
PMU1CRU_RESET_OFFSET(SRST_H_FSPI1, 0, 2),
PMU1CRU_RESET_OFFSET(SRST_H_XIP_FSPI1, 0, 3),
PMU1CRU_RESET_OFFSET(SRST_S_1X_FSPI1, 0, 4),
PMU1CRU_RESET_OFFSET(SRST_P_IOC_PMUIO1, 0, 5),
PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 0, 6),
PMU1CRU_RESET_OFFSET(SRST_P_AUDIO_ADC_PMU, 0, 7),
PMU1CRU_RESET_OFFSET(SRST_M_AUDIO_ADC_PMU, 0, 8),
PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 9),
PMU1CRU_RESET_OFFSET(SRST_P_LPDMA, 1, 0),
PMU1CRU_RESET_OFFSET(SRST_A_LPDMA, 1, 1),
PMU1CRU_RESET_OFFSET(SRST_H_LPSAI, 1, 2),
PMU1CRU_RESET_OFFSET(SRST_M_LPSAI, 1, 3),
PMU1CRU_RESET_OFFSET(SRST_P_AOA_TDD, 1, 4),
PMU1CRU_RESET_OFFSET(SRST_P_AOA_FE, 1, 5),
PMU1CRU_RESET_OFFSET(SRST_P_AOA_AAD, 1, 6),
PMU1CRU_RESET_OFFSET(SRST_P_AOA_APB, 1, 7),
PMU1CRU_RESET_OFFSET(SRST_P_AOA_SRAM, 1, 8),