PLL3
[PLL3] = &pll3.clkr,
[PLL3] = &pll3.clkr,
[PLL3] = &pll3.clkr,
PLL(PLL3, "pll3", ref3_parents, 0, RCC_PLL3CR, RCC_RCK3SELR),
.hw.init = CLK_HW_INIT_INDEX("ck_ker_gpu", PLL3, &clk_stm32_gate_ops, 0),
REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
#define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
pll = PLL3 | PLL2;
pll = PLL3 | PLL2 | PLL0;
pll = PLL3;
pll = PLL3 | PLL2 | PLL1;
pll = PLL3 | PLL2 | PLL1 | PLL0;