PLATFORM_PLL
plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
if (cg->coreclk && idx != PLATFORM_PLL) {
case PLATFORM_PLL:
if (idx == PLATFORM_PLL)
((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL))
if (idx != PLATFORM_PLL && i >= 4)
legacy_pll_init(np, PLATFORM_PLL);
pll = &cg->pll[PLATFORM_PLL];
{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
[5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
[5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;
.pll_mask = BIT(PLATFORM_PLL) |
.pll_mask = BIT(PLATFORM_PLL) |
.pll_mask = BIT(PLATFORM_PLL) |
.pll_mask = BIT(PLATFORM_PLL) |
.pll_mask = BIT(PLATFORM_PLL) |
.pll_mask = BIT(PLATFORM_PLL) |
.pll_mask = BIT(PLATFORM_PLL) |
.pll_mask = BIT(PLATFORM_PLL) | BIT(CGA_PLL1),
.pll_mask = BIT(PLATFORM_PLL) |
.pll_mask = BIT(PLATFORM_PLL) |
.pll_mask = BIT(PLATFORM_PLL) |
.pll_mask = BIT(PLATFORM_PLL) |
.pll_mask = BIT(PLATFORM_PLL) |
.pll_mask = BIT(PLATFORM_PLL) |
.pll_mask = BIT(PLATFORM_PLL) |
.pll_mask = BIT(PLATFORM_PLL) | BIT(CGA_PLL1),
.pll_mask = BIT(PLATFORM_PLL) |
.pll_mask = BIT(PLATFORM_PLL) |
.pll_mask = BIT(PLATFORM_PLL) |