PMC
writel(0, pmu->base + PMC(counter) + 0x4);
writel(0, pmu->base + PMC(counter));
writel(0, pmu->base + PMC(counter));
val = readl_relaxed(pmu->base + PMC(counter));
val_upper = readl_relaxed(pmu->base + PMC(counter) + 0x4);
val_lower = readl_relaxed(pmu->base + PMC(counter));
} while (val_upper != readl_relaxed(pmu->base + PMC(counter) + 0x4));
reg8 = readb(pctrl->base + PMC(off));
pctrl->data->pmc_writeb(pctrl, reg8, PMC(off));
if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) {
reg8 = readb(pctrl->base + PMC(off));
RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]);
pctrl->data->pmc_writeb(pctrl, cache->pmc[port], PMC(off));
writeb(pmc, pctrl->base + PMC(off));
writeb(pmc, pctrl->base + PMC(off));
reg = readb(pctrl->base + PMC(off));
reg = readb(pctrl->base + PMC(off));
writeb(reg & ~BIT(pin), pctrl->base + PMC(off));
reg = readb(pctrl->base + PMC(off));
writeb(reg | BIT(pin), pctrl->base + PMC(off));
u8 reg = rzt2h_pinctrl_readb(pctrl, port, PMC(port));
rzt2h_pinctrl_writeb(pctrl, port, reg, PMC(port));
if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit)) {
tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF;
NV_WR32(par->PMC, 0x10F0, tmp_pmc);
NV_WR32(par->PMC, 0x1700,
NV_WR32(par->PMC, 0x1704, 0);
NV_WR32(par->PMC, 0x1708, 0);
NV_WR32(par->PMC, 0x170C,
pll = NV_RD32(par->PMC, 0x4020);
pll = NV_RD32(par->PMC, 0x4024);
NV_WR32(par->PMC, 0x8704, 1);
NV_WR32(par->PMC, 0x8140, 0);
NV_WR32(par->PMC, 0x8920, 0);
NV_WR32(par->PMC, 0x8924, 0);
NV_WR32(par->PMC, 0x8908, par->FbMapSize - 1);
NV_WR32(par->PMC, 0x890C, par->FbMapSize - 1);
NV_WR32(par->PMC, 0x1588, 0);
pll = NV_RD32(par->PMC, 0x4000);
pll = NV_RD32(par->PMC, 0x4004);
NV_WR32(par->PMC, 0x0140, 0x00000000);
NV_WR32(par->PMC, 0x0200, 0xFFFF00FF);
NV_WR32(par->PMC, 0x0200, 0xFFFFFFFF);
if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) {
NV_WR32(par->PMC, 0x0004, 0x01000001);
par->PMC = par->REGS + (0x00000000 / 4);
volatile u32 __iomem *PMC;
tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF;
NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc);
if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
&& ((NV_RD32(chip->PMC, 0x00000000)&0x0F)>=0x02)) {
if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
&& ((NV_RD32(chip->PMC,0x00000000)&0x0F) >= 0x02)) {
par->riva.PMC =
#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
#define PMC_Read(reg) DEVICE_READ(PMC,reg)
#define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
#define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
#define PMC_Read(reg) DEVICE_READ(PMC,reg)
#define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
#define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
LOAD_FIXED_STATE(Riva,PMC);
NV_WR32(chip->PMC, 0x00008704, 1);
NV_WR32(chip->PMC, 0x00008140, 0);
NV_WR32(chip->PMC, 0x00008920, 0);
NV_WR32(chip->PMC, 0x00008924, 0);
NV_WR32(chip->PMC, 0x00008908, 0x01ffffff);
NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff);
NV_WR32(chip->PMC, 0x00001588, 0);
NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01);
if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
&& ((NV_RD32(chip->PMC, 0x00000000) & 0x0F) >= 0x02))
if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001))
NV_WR32(chip->PMC, 0x00000004, 0x01000001);
volatile U032 __iomem *PMC;