PLL_STATUS
return readl_poll_timeout(pll->base + PLL_STATUS, val,
ana_mfn = readl_relaxed(pll->base + PLL_STATUS);
while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK))
regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val);
DSI_FLD_GET(PLL_STATUS, 0, 0),
if (wait_for_bit_change(base + PLL_STATUS, 0, 1) != 1)
u32 v = readl_relaxed(pll->base + PLL_STATUS);
l = readl_relaxed(base + PLL_STATUS);
if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
DSI_FLD_GET(PLL_STATUS, 0, 0),
if (wait_for_bit_change(base + PLL_STATUS, 0, 1) != 1)
u32 v = readl_relaxed(pll->base + PLL_STATUS);
if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {