PLLM_OUT
clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
clk_base + PLLM_OUT, 1, 0,
clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
clk_base + PLLM_OUT, 1, 0,
clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
clk_base + PLLM_OUT, 1, 0,