PLL_LOCK
if (!(ioread32(clk->lock) & PLL_LOCK))
val & PLL_LOCK, 120,
if (intel_de_wait_for_set_ms(display, enable_reg, PLL_LOCK, 1))
if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_LOCK, 1))
if (intel_de_wait_for_set_ms(display, enable_reg, PLL_LOCK, 5))
if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_LOCK, 5))
PIS(PLL_LOCK);
PIS(PLL_LOCK),
BIT(u3pll_ctrl[PLL_LOCK]));
BIT(u2pll_ctrl[PLL_LOCK]));
[PLL_LOCK] = 3,
[PLL_LOCK] = 6,
sts, (sts & PLL_LOCK), 1000, 20000);
if (val & PLL_LOCK)
if ((val & PLL_LOCK) && phy->mode == PIPE3_MODE_SATA)
val & PLL_LOCK, 10, 100);
return regmap_test_bits(clk->regmap, GPR_REG1, PLL_LOCK);
PIS(PLL_LOCK);
PIS(PLL_LOCK),