drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

473

head_pipe_in_stage = stage * PIPES_PER_STAGE;

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

474

for (i = 0; i < PIPES_PER_STAGE; i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

478

lms_in_pair = min(cstate->num_mixers - (stage * PIPES_PER_STAGE),

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

479

PIPES_PER_STAGE);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

576

&stage_cfg[i / PIPES_PER_STAGE]);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

580

&stage_cfg[i / PIPES_PER_STAGE]);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

523

pipes_per_stage = PIPES_PER_STAGE;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h

31

enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE];

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h

33

[DPU_STAGE_MAX][PIPES_PER_STAGE];

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

236

u32 src_sel[PIPES_PER_STAGE];

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

297

pipes_per_stage = PIPES_PER_STAGE;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h

39

#define PIPES_PER_PLANE (PIPES_PER_STAGE * STAGES_PER_PLANE)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1040

pipe_idx = stage_index * PIPES_PER_STAGE;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1299

pipe = &pstate->pipe[i * PIPES_PER_STAGE];

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1300

pipe_cfg = &pstate->pipe_cfg[i * PIPES_PER_STAGE];

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1603

if (i % PIPES_PER_STAGE == 0)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

915

int cfg_idx = stage_id * PIPES_PER_STAGE;