drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1376

#define MAX_CHANNELS_PER_CRTC PIPES_PER_PLANE

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1764

for (i = 0; i < PIPES_PER_PLANE; i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1064

for (i = 0; i < PIPES_PER_PLANE; i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1272

for (i = 0; i < PIPES_PER_PLANE; i++)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1440

for (i = 0; i < PIPES_PER_PLANE; i++)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1562

for (i = 0; i < PIPES_PER_PLANE; i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1576

for (i = 0; i < PIPES_PER_PLANE; i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1595

for (i = 0; i < PIPES_PER_PLANE; i += 1) {

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1714

for (i = 0; i < PIPES_PER_PLANE; i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1771

for (i = 0; i < PIPES_PER_PLANE; i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

636

for (i = 0; i < PIPES_PER_PLANE; i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h

34

struct dpu_sw_pipe pipe[PIPES_PER_PLANE];

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h

35

struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_PLANE];