PLL_ENABLE
reg &= ~PLL_ENABLE;
parent_name, 0, mode_reg, PLL_ENABLE, 0, lock);
if (val & PLL_ENABLE) {
if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
if (val & PLL_ENABLE) {
if (val & PLL_ENABLE) {
if (val & PLL_ENABLE) {
reg |= PLL_ENABLE;
if (!(reg & PLL_ENABLE)) {
if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) {
if (val & PLL_ENABLE) {
PLL_ENABLE) {
if (val & PLL_ENABLE) {
if (!(val & PLL_ENABLE))
if (!(val & PLL_ENABLE))
if (!(val & PLL_ENABLE))
intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
intel_de_rmw(display, enable_reg, PLL_ENABLE, 0);
intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
intel_de_rmw(display, enable_reg, PLL_ENABLE, 0);
[PLL_ENABLE] = REG_FIELD(WIZ_PLL_CTRL, 29, 31),
ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_ENABLE_STATE);
ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_DISABLE_STATE);
snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
PLL_ENABLE, PLL_ENABLE);
PLL_ENABLE, PLL_ENABLE);
PLL_ENABLE, 0);