PLLE_AUX
.aux_reg = PLLE_AUX,
clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
.aux_reg = PLLE_AUX,
.aux_reg = PLLE_AUX,
clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
value = readl_relaxed(clk_base + PLLE_AUX);
value = readl_relaxed(clk_base + PLLE_AUX);
writel_relaxed(value, clk_base + PLLE_AUX);
writel_relaxed(value, clk_base + PLLE_AUX);
clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
clk_base + PLLE_AUX, 2, 1, 0, NULL);