PLLD_BASE
clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
.base_reg = PLLD_BASE,
plld_base = readl(clk_base + PLLD_BASE);
writel(plld_base, clk_base + PLLD_BASE);
.base_reg = PLLD_BASE,
.base_reg = PLLD_BASE,
.base_reg = PLLD_BASE,
CLK_SET_RATE_PARENT, clk_base + PLLD_BASE,
value = readl(clk_base + PLLD_BASE);
writel(value, clk_base + PLLD_BASE);
csi_src = readl_relaxed(clk_base + PLLD_BASE);
writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE);
writel_relaxed(csi_src, clk_base + PLLD_BASE);
clk_base + PLLD_BASE, 26, 0, &pll_d_lock);
.base_reg = PLLD_BASE,