PLLC_OUT
clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
clk_base + PLLC_OUT, 1, 0,
clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
clk_base + PLLC_OUT, 1, 0,
clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
clk_base + PLLC_OUT, 1, 0,
clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,