PLLA_OUT
clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
MUX_PG(cdev1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, 0x14, 4, 0x88, 2, 0xa8, 0),