PL080_CONFIG_ENABLE
writel(PL080_CONFIG_ENABLE, pl08x->base + FTDMAC020_CSR);
writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
(val & PL080_CONFIG_ENABLE))
writel(val | PL080_CONFIG_ENABLE, phychan->reg_config);
val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |