drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

155

*tmds_div = val_tmds_div == 0 ? PIXEL_RATE_DIV_BY_2 : PIXEL_RATE_DIV_BY_4;

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

170

if (tmds_div != PIXEL_RATE_DIV_BY_2 && tmds_div != PIXEL_RATE_DIV_BY_4) {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

179

reg_val = tmds_div == PIXEL_RATE_DIV_BY_4 ? 1 : 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

345

*k2_div = PIXEL_RATE_DIV_BY_4;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

352

*k2_div = PIXEL_RATE_DIV_BY_4;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1209

*k2_div = PIXEL_RATE_DIV_BY_4;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1216

*k2_div = PIXEL_RATE_DIV_BY_4;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

715

*tmds_div = PIXEL_RATE_DIV_BY_4;