drivers/gpu/drm/i915/display/g4x_dp.c

1391

intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);

drivers/gpu/drm/i915/display/g4x_dp.c

436

if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B && port != PORT_A) {

drivers/gpu/drm/i915/display/g4x_hdmi.c

398

if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) {

drivers/gpu/drm/i915/display/g4x_hdmi.c

748

intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);

drivers/gpu/drm/i915/display/i9xx_plane.c

1096

if (display->platform.cherryview && pipe == PIPE_B) {

drivers/gpu/drm/i915/display/i9xx_plane.c

1198

pipe == PIPE_B && val & DISP_MIRROR)

drivers/gpu/drm/i915/display/i9xx_wm.c

1915

case PIPE_B:

drivers/gpu/drm/i915/display/i9xx_wm.c

300

case PIPE_B:

drivers/gpu/drm/i915/display/i9xx_wm.c

3370

if (dirty & WM_DIRTY_PIPE(PIPE_B))

drivers/gpu/drm/i915/display/i9xx_wm.c

3371

intel_de_write(display, WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);

drivers/gpu/drm/i915/display/i9xx_wm.c

3671

wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);

drivers/gpu/drm/i915/display/i9xx_wm.c

3672

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);

drivers/gpu/drm/i915/display/i9xx_wm.c

3679

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);

drivers/gpu/drm/i915/display/i9xx_wm.c

3711

wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);

drivers/gpu/drm/i915/display/i9xx_wm.c

3712

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);

drivers/gpu/drm/i915/display/i9xx_wm.c

3725

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);

drivers/gpu/drm/i915/display/i9xx_wm.c

3726

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);

drivers/gpu/drm/i915/display/i9xx_wm.c

3741

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;

drivers/gpu/drm/i915/display/i9xx_wm.c

3742

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;

drivers/gpu/drm/i915/display/i9xx_wm.c

3743

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;

drivers/gpu/drm/i915/display/i9xx_wm.c

3749

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);

drivers/gpu/drm/i915/display/i9xx_wm.c

3750

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);

drivers/gpu/drm/i915/display/i9xx_wm.c

3754

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;

drivers/gpu/drm/i915/display/i9xx_wm.c

3755

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;

drivers/gpu/drm/i915/display/i9xx_wm.c

3756

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;

drivers/gpu/drm/i915/display/i9xx_wm.c

816

FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |

drivers/gpu/drm/i915/display/i9xx_wm.c

817

FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |

drivers/gpu/drm/i915/display/i9xx_wm.c

823

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |

drivers/gpu/drm/i915/display/i9xx_wm.c

866

FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |

drivers/gpu/drm/i915/display/i9xx_wm.c

867

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |

drivers/gpu/drm/i915/display/i9xx_wm.c

878

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |

drivers/gpu/drm/i915/display/i9xx_wm.c

879

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));

drivers/gpu/drm/i915/display/i9xx_wm.c

891

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |

drivers/gpu/drm/i915/display/i9xx_wm.c

892

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |

drivers/gpu/drm/i915/display/i9xx_wm.c

893

FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |

drivers/gpu/drm/i915/display/i9xx_wm.c

899

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |

drivers/gpu/drm/i915/display/i9xx_wm.c

900

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));

drivers/gpu/drm/i915/display/i9xx_wm.c

903

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |

drivers/gpu/drm/i915/display/i9xx_wm.c

904

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |

drivers/gpu/drm/i915/display/i9xx_wm.c

905

FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |

drivers/gpu/drm/i915/display/icl_dsi.c

1250

if (DISPLAY_VER(display) == 11 && pipe == PIPE_B)

drivers/gpu/drm/i915/display/icl_dsi.c

1603

if (DISPLAY_VER(display) == 11 && pipe == PIPE_B &&

drivers/gpu/drm/i915/display/icl_dsi.c

1744

*pipe = PIPE_B;

drivers/gpu/drm/i915/display/icl_dsi.c

836

case PIPE_B:

drivers/gpu/drm/i915/display/intel_backlight.c

1402

if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))

drivers/gpu/drm/i915/display/intel_backlight.c

189

if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))

drivers/gpu/drm/i915/display/intel_color.c

4274

return pipe == PIPE_A || pipe == PIPE_B;

drivers/gpu/drm/i915/display/intel_ddi.c

2491

return BIT(PIPE_A) | BIT(PIPE_B);

drivers/gpu/drm/i915/display/intel_ddi.c

567

case PIPE_B:

drivers/gpu/drm/i915/display/intel_ddi.c

838

*pipe_mask = BIT(PIPE_B);

drivers/gpu/drm/i915/display/intel_display.c

2053

if (display->platform.cherryview && pipe == PIPE_B) {

drivers/gpu/drm/i915/display/intel_display.c

2738

(pipe == PIPE_B || pipe == PIPE_C))

drivers/gpu/drm/i915/display/intel_display.c

3472

pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);

drivers/gpu/drm/i915/display/intel_display.c

3474

pipes = BIT(PIPE_B) | BIT(PIPE_C);

drivers/gpu/drm/i915/display/intel_display.c

3790

trans_pipe = PIPE_B;

drivers/gpu/drm/i915/display/intel_display.c

8419

intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK);

drivers/gpu/drm/i915/display/intel_display_device.c

1073

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/intel_display_device.c

1162

BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)

drivers/gpu/drm/i915/display/intel_display_device.c

1340

BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \

drivers/gpu/drm/i915/display/intel_display_device.c

1363

BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/intel_display_device.c

176

[PIPE_B] = CURSOR_B_OFFSET, \

drivers/gpu/drm/i915/display/intel_display_device.c

1784

display_runtime->num_scalers[PIPE_B] = 2;

drivers/gpu/drm/i915/display/intel_display_device.c

1808

display_runtime->num_sprites[PIPE_B] = 2;

drivers/gpu/drm/i915/display/intel_display_device.c

182

[PIPE_B] = CURSOR_B_OFFSET, \

drivers/gpu/drm/i915/display/intel_display_device.c

1858

display_runtime->pipe_mask &= ~BIT(PIPE_B);

drivers/gpu/drm/i915/display/intel_display_device.c

189

[PIPE_B] = IVB_CURSOR_B_OFFSET, \

drivers/gpu/drm/i915/display/intel_display_device.c

196

[PIPE_B] = IVB_CURSOR_B_OFFSET, \

drivers/gpu/drm/i915/display/intel_display_device.c

241

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

drivers/gpu/drm/i915/display/intel_display_device.c

304

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

drivers/gpu/drm/i915/display/intel_display_device.c

393

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

drivers/gpu/drm/i915/display/intel_display_device.c

450

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

drivers/gpu/drm/i915/display/intel_display_device.c

479

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),

drivers/gpu/drm/i915/display/intel_display_device.c

504

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/intel_display_device.c

533

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),

drivers/gpu/drm/i915/display/intel_display_device.c

581

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/intel_display_device.c

634

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/intel_display_device.c

654

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/intel_display_device.c

678

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/intel_display_device.c

828

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \

drivers/gpu/drm/i915/display/intel_display_device.c

903

.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \

drivers/gpu/drm/i915/display/intel_display_device.c

995

BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \

drivers/gpu/drm/i915/display/intel_display_irq.c

1354

pipe = PIPE_B;

drivers/gpu/drm/i915/display/intel_display_irq.c

1832

case PIPE_B:

drivers/gpu/drm/i915/display/intel_display_irq.c

1992

i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2007

i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

411

i915_enable_pipestat(display, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

565

case PIPE_B:

drivers/gpu/drm/i915/display/intel_display_irq.c

720

intel_pch_fifo_underrun_irq_handler(display, PIPE_B);

drivers/gpu/drm/i915/display/intel_display_irq.c

730

case PIPE_B:

drivers/gpu/drm/i915/display/intel_display_irq.c

851

case PIPE_B:

drivers/gpu/drm/i915/display/intel_display_limits.h

35

TRANSCODER_B = PIPE_B,

drivers/gpu/drm/i915/display/intel_display_power_map.c

1073

.irq_pipe_mask = BIT(PIPE_B),

drivers/gpu/drm/i915/display/intel_display_power_map.c

1168

.irq_pipe_mask = BIT(PIPE_B),

drivers/gpu/drm/i915/display/intel_display_power_map.c

1344

.irq_pipe_mask = BIT(PIPE_B),

drivers/gpu/drm/i915/display/intel_display_power_map.c

150

.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/intel_display_power_map.c

1501

.irq_pipe_mask = BIT(PIPE_B),

drivers/gpu/drm/i915/display/intel_display_power_map.c

1668

.irq_pipe_mask = BIT(PIPE_B),

drivers/gpu/drm/i915/display/intel_display_power_map.c

1741

.irq_pipe_mask = BIT(PIPE_B),

drivers/gpu/drm/i915/display/intel_display_power_map.c

394

.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/intel_display_power_map.c

473

.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/intel_display_power_map.c

576

.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/intel_display_power_map.c

752

.irq_pipe_mask = BIT(PIPE_B),

drivers/gpu/drm/i915/display/intel_display_power_map.c

918

.irq_pipe_mask = BIT(PIPE_B),

drivers/gpu/drm/i915/display/intel_display_power_well.c

1105

if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1106

i830_enable_pipe(display, PIPE_B);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1112

i830_disable_pipe(display, PIPE_B);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1120

intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE;

drivers/gpu/drm/i915/display/intel_display_power_well.c

1412

(intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1539

assert_pll_disabled(display, PIPE_B);

drivers/gpu/drm/i915/display/intel_dmc.c

500

MTL_PIPEDMC_GATING_DIS(PIPE_B));

drivers/gpu/drm/i915/display/intel_dmc.c

934

PIPE_B_DMC_W2_PTS_CONFIG_SELECT(PIPE_B) |

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1048

if (pipe != PIPE_B) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1144

if (pipe == PIPE_B)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

694

case PIPE_B:

drivers/gpu/drm/i915/display/intel_dpio_phy.c

710

case PIPE_B:

drivers/gpu/drm/i915/display/intel_dpio_phy.c

884

if (ch == DPIO_CH0 && pipe == PIPE_B)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

896

if (pipe != PIPE_B) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

917

if (pipe == PIPE_B)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

926

if (pipe == PIPE_B)

drivers/gpu/drm/i915/display/intel_dpio_phy.c

939

if (pipe == PIPE_B)

drivers/gpu/drm/i915/display/intel_dpll.c

1925

if (pipe == PIPE_B)

drivers/gpu/drm/i915/display/intel_dpll.c

2181

intel_de_write(display, DPLL_MD(display, PIPE_B),

drivers/gpu/drm/i915/display/intel_dpll.c

2191

(intel_de_read(display, DPLL(display, PIPE_B)) &

drivers/gpu/drm/i915/display/intel_fdi.c

162

crtc = intel_crtc_for_pipe(display, PIPE_B);

drivers/gpu/drm/i915/display/intel_fdi.c

173

BIT(PIPE_B));

drivers/gpu/drm/i915/display/intel_fdi.c

223

case PIPE_B:

drivers/gpu/drm/i915/display/intel_fdi.c

248

other_crtc = intel_crtc_for_pipe(display, PIPE_B);

drivers/gpu/drm/i915/display/intel_fdi.c

258

*pipe_to_reduce = PIPE_B;

drivers/gpu/drm/i915/display/intel_fdi.c

398

intel_de_read(display, FDI_RX_CTL(PIPE_B)) &

drivers/gpu/drm/i915/display/intel_fdi.c

422

case PIPE_B:

drivers/gpu/drm/i915/display/intel_lvds.c

932

encoder->pipe_mask = BIT(PIPE_B);

drivers/gpu/drm/i915/display/intel_pch_display.c

56

HAS_PCH_IBX(display) && !state && port_pipe == PIPE_B,

drivers/gpu/drm/i915/display/intel_pch_display.c

75

HAS_PCH_IBX(display) && !state && port_pipe == PIPE_B,

drivers/gpu/drm/i915/display/intel_pfit.c

723

pipe = PIPE_B;

drivers/gpu/drm/i915/display/intel_pipe_crc.c

181

case PIPE_B:

drivers/gpu/drm/i915/display/intel_pipe_crc.c

242

case PIPE_B:

drivers/gpu/drm/i915/display/intel_pps.c

1163

if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))

drivers/gpu/drm/i915/display/intel_pps.c

1253

if (pipe != PIPE_A && pipe != PIPE_B)

drivers/gpu/drm/i915/display/intel_pps.c

1256

if (pipe != PIPE_A && pipe != PIPE_B)

drivers/gpu/drm/i915/display/intel_pps.c

174

unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);

drivers/gpu/drm/i915/display/intel_pps.c

302

for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {

drivers/gpu/drm/i915/display/intel_pps.c

49

case PIPE_B:

drivers/gpu/drm/i915/display/intel_psr.c

1232

return pipe <= PIPE_B && port <= PORT_B;

drivers/gpu/drm/i915/display/intel_psr.c

1786

to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B)

drivers/gpu/drm/i915/display/intel_sdvo.c

1859

if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) {

drivers/gpu/drm/i915/display/intel_sprite.c

1625

if (display->platform.cherryview && pipe == PIPE_B) {

drivers/gpu/drm/i915/display/intel_sprite.c

1688

if (display->platform.cherryview && pipe == PIPE_B) {

drivers/gpu/drm/i915/display/intel_sprite.c

403

if (display->platform.cherryview && pipe == PIPE_B)

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

224

#define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

227

#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

230

#define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

233

#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

249

#define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

252

#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

255

#define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

258

#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

275

#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

278

#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

281

#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

284

#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

303

#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

306

#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

309

#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

312

#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

328

#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

33

#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

331

#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

334

#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

337

#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

353

#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

356

#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

359

#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

362

#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

49

#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

66

#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

69

#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

72

#define _ICL_DSC0_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

75

#define _ICL_DSC1_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

78

#define _BMG_DSC2_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \

drivers/gpu/drm/i915/display/intel_vrr.c

367

((pipe == PIPE_A) || (pipe == PIPE_B)));

drivers/gpu/drm/i915/display/skl_watermark.c

1001

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

1004

[PIPE_B] = BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

1024

.active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

1026

[PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

1032

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

1035

[PIPE_B] = BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

1056

.active_pipes = BIT(PIPE_B),

drivers/gpu/drm/i915/display/skl_watermark.c

1058

[PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4),

drivers/gpu/drm/i915/display/skl_watermark.c

1070

.active_pipes = BIT(PIPE_B),

drivers/gpu/drm/i915/display/skl_watermark.c

1072

[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),

drivers/gpu/drm/i915/display/skl_watermark.c

1077

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),

drivers/gpu/drm/i915/display/skl_watermark.c

1080

[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),

drivers/gpu/drm/i915/display/skl_watermark.c

1097

.active_pipes = BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/skl_watermark.c

1099

[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),

drivers/gpu/drm/i915/display/skl_watermark.c

1104

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/skl_watermark.c

1107

[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),

drivers/gpu/drm/i915/display/skl_watermark.c

1125

.active_pipes = BIT(PIPE_B) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

1127

[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),

drivers/gpu/drm/i915/display/skl_watermark.c

1132

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

1135

[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),

drivers/gpu/drm/i915/display/skl_watermark.c

1155

.active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

1157

[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),

drivers/gpu/drm/i915/display/skl_watermark.c

1163

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

1166

[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),

drivers/gpu/drm/i915/display/skl_watermark.c

3386

case PIPE_B:

drivers/gpu/drm/i915/display/skl_watermark.c

3388

active_pipes &= BIT(PIPE_B) | BIT(PIPE_C);

drivers/gpu/drm/i915/display/skl_watermark.c

766

.active_pipes = BIT(PIPE_B),

drivers/gpu/drm/i915/display/skl_watermark.c

768

[PIPE_B] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

772

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),

drivers/gpu/drm/i915/display/skl_watermark.c

775

[PIPE_B] = BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

792

.active_pipes = BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/skl_watermark.c

794

[PIPE_B] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

799

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/skl_watermark.c

802

[PIPE_B] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

829

.active_pipes = BIT(PIPE_B),

drivers/gpu/drm/i915/display/skl_watermark.c

831

[PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

835

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),

drivers/gpu/drm/i915/display/skl_watermark.c

838

[PIPE_B] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

855

.active_pipes = BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/skl_watermark.c

857

[PIPE_B] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

862

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/skl_watermark.c

865

[PIPE_B] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

883

.active_pipes = BIT(PIPE_B) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

885

[PIPE_B] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

890

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

893

[PIPE_B] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

913

.active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

915

[PIPE_B] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

921

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

924

[PIPE_B] = BIT(DBUF_S1),

drivers/gpu/drm/i915/display/skl_watermark.c

940

.active_pipes = BIT(PIPE_B),

drivers/gpu/drm/i915/display/skl_watermark.c

942

[PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

946

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),

drivers/gpu/drm/i915/display/skl_watermark.c

949

[PIPE_B] = BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

966

.active_pipes = BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/skl_watermark.c

968

[PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

973

.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),

drivers/gpu/drm/i915/display/skl_watermark.c

976

[PIPE_B] = BIT(DBUF_S2),

drivers/gpu/drm/i915/display/skl_watermark.c

994

.active_pipes = BIT(PIPE_B) | BIT(PIPE_D),

drivers/gpu/drm/i915/display/skl_watermark.c

996

[PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),

drivers/gpu/drm/i915/display/vlv_dsi.c

1965

encoder->pipe_mask = BIT(PIPE_B);

drivers/gpu/drm/i915/display/vlv_dsi.c

972

TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE;

drivers/gpu/drm/i915/display/vlv_dsi.c

997

*pipe = port == PORT_A ? PIPE_A : PIPE_B;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1298

[1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},

drivers/gpu/drm/i915/gvt/cmd_parser.c

1300

[3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},

drivers/gpu/drm/i915/gvt/cmd_parser.c

1357

info->pipe = PIPE_B;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1371

info->pipe = PIPE_B;

drivers/gpu/drm/i915/gvt/display.c

64

pipe = PIPE_B;

drivers/gpu/drm/i915/gvt/display.c

645

[PIPE_B] = PIPE_B_VBLANK,

drivers/gpu/drm/i915/gvt/handlers.c

1028

calc_index(offset, DSPSURF(display, PIPE_A), DSPSURF(display, PIPE_B), DSPSURF(display, PIPE_C))

drivers/gpu/drm/i915/gvt/handlers.c

1052

calc_index(offset, SPRSURF(PIPE_A), SPRSURF(PIPE_B), SPRSURF(PIPE_C))

drivers/gpu/drm/i915/gvt/handlers.c

2311

MMIO_DH(DSPSURF(display, PIPE_B), D_ALL, NULL, pri_surf_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2312

MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2320

MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2321

MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2344

MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2347

MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);

drivers/gpu/drm/i915/gvt/handlers.c

2350

MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);

drivers/gpu/drm/i915/gvt/handlers.c

2503

MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2505

MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2507

MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2642

MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);

drivers/gpu/drm/i915/gvt/handlers.c

2643

MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);

drivers/gpu/drm/i915/gvt/handlers.c

2649

MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);

drivers/gpu/drm/i915/gvt/handlers.c

2650

MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);

drivers/gpu/drm/i915/gvt/handlers.c

2656

MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);

drivers/gpu/drm/i915/gvt/handlers.c

2657

MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);

drivers/gpu/drm/i915/gvt/handlers.c

2666

MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2667

MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2668

MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2669

MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2677

MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2684

MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2685

MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2686

MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2693

MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2701

MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2702

MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2703

MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2704

MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2716

MMIO_DH(PLANE_AUX_DIST(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2717

MMIO_DH(PLANE_AUX_DIST(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2718

MMIO_DH(PLANE_AUX_DIST(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2719

MMIO_DH(PLANE_AUX_DIST(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2731

MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2732

MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2733

MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2734

MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

914

calc_index(offset, FDI_RX_CTL(PIPE_A), FDI_RX_CTL(PIPE_B), FDI_RX_CTL(PIPE_C))

drivers/gpu/drm/i915/gvt/handlers.c

917

calc_index(offset, FDI_TX_CTL(PIPE_A), FDI_TX_CTL(PIPE_B), FDI_TX_CTL(PIPE_C))

drivers/gpu/drm/i915/gvt/handlers.c

920

calc_index(offset, FDI_RX_IMR(PIPE_A), FDI_RX_IMR(PIPE_B), FDI_RX_IMR(PIPE_C))

drivers/gpu/drm/i915/gvt/interrupt.c

512

DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B));

drivers/gpu/drm/i915/gvt/reg.h

70

(((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \

drivers/gpu/drm/i915/gvt/reg.h

79

(((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1000

MMIO_D(PLANE_WM_TRANS(PIPE_B, 1));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1001

MMIO_D(PLANE_WM_TRANS(PIPE_B, 2));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1006

MMIO_D(CUR_WM_TRANS(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1012

MMIO_D(PLANE_NV12_BUF_CFG(PIPE_B, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1013

MMIO_D(PLANE_NV12_BUF_CFG(PIPE_B, 1));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1014

MMIO_D(PLANE_NV12_BUF_CFG(PIPE_B, 2));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1015

MMIO_D(PLANE_NV12_BUF_CFG(PIPE_B, 3));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1024

MMIO_D(PLANE_AUX_DIST(PIPE_B, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1025

MMIO_D(PLANE_AUX_DIST(PIPE_B, 1));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1026

MMIO_D(PLANE_AUX_DIST(PIPE_B, 2));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1027

MMIO_D(PLANE_AUX_DIST(PIPE_B, 3));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1036

MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1037

MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 1));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1038

MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 2));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1039

MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 3));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1045

MMIO_D(PLANE_CTL(PIPE_B, 2));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1048

MMIO_D(PLANE_SURF(PIPE_B, 2));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1090

MMIO_D(PLANE_KEYVAL(PIPE_B, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1093

MMIO_D(PLANE_KEYMAX(PIPE_B, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1096

MMIO_D(PLANE_KEYMSK(PIPE_B, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

140

MMIO_D(PIPEDSL(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

148

MMIO_D(PIPESTAT(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

152

MMIO_D(PIPE_FLIPCOUNT_G4X(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

156

MMIO_D(PIPE_FRMCOUNT_G4X(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

160

MMIO_D(CURCNTR(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

163

MMIO_D(CURPOS(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

166

MMIO_D(CURBASE(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

169

MMIO_D(CUR_FBC_CTL(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

187

MMIO_D(DSPCNTR(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

188

MMIO_D(DSPADDR(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

189

MMIO_D(DSPSTRIDE(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

190

MMIO_D(DSPPOS(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

191

MMIO_D(DSPSIZE(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

192

MMIO_D(DSPSURF(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

193

MMIO_D(DSPOFFSET(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

194

MMIO_D(DSPSURFLIVE(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

195

MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

218

MMIO_D(SPRCTL(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

219

MMIO_D(SPRLINOFF(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

220

MMIO_D(SPRSTRIDE(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

221

MMIO_D(SPRPOS(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

222

MMIO_D(SPRSIZE(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

223

MMIO_D(SPRKEYVAL(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

224

MMIO_D(SPRKEYMSK(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

225

MMIO_D(SPRSURF(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

226

MMIO_D(SPRKEYMAX(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

227

MMIO_D(SPROFFSET(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

228

MMIO_D(SPRSCALE(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

229

MMIO_D(SPRSURFLIVE(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

230

MMIO_D(REG_50080(PIPE_B, PLANE_SPRITE0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

316

MMIO_D(PF_CTL(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

317

MMIO_D(PF_WIN_SZ(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

318

MMIO_D(PF_WIN_POS(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

319

MMIO_D(PF_VSCALE(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

320

MMIO_D(PF_HSCALE(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

327

MMIO_D(WM0_PIPE_ILK(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

346

MMIO_D(FDI_RX_IIR(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

349

MMIO_D(FDI_RX_IMR(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

352

MMIO_D(FDI_RX_CTL(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

377

MMIO_D(TRANS_DP_CTL(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

382

MMIO_D(TVIDEO_DIP_CTL(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

383

MMIO_D(TVIDEO_DIP_DATA(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

384

MMIO_D(TVIDEO_DIP_GCP(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

454

MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

455

MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

456

MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

457

MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

458

MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

459

MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

460

MMIO_D(PIPE_CSC_MODE(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

461

MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

462

MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

463

MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

464

MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

465

MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

466

MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

483

MMIO_D(PREC_PAL_INDEX(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

484

MMIO_D(PREC_PAL_DATA(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

485

MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

495

MMIO_D(WM_LINETIME(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

517

MMIO_D(GAMMA_MODE(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

712

MMIO_F(LGC_PALETTE(PIPE_B, 0), 1024);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

767

MMIO_D(GEN8_DE_PIPE_IMR(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

768

MMIO_D(GEN8_DE_PIPE_IER(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

769

MMIO_D(GEN8_DE_PIPE_IIR(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

770

MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

815

MMIO_D(PIPE_MISC(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

834

MMIO_D(CHICKEN_PIPESL_1(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

953

MMIO_D(SKL_PS_WIN_POS(PIPE_B, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

954

MMIO_D(SKL_PS_WIN_POS(PIPE_B, 1));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

959

MMIO_D(SKL_PS_WIN_SZ(PIPE_B, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

960

MMIO_D(SKL_PS_WIN_SZ(PIPE_B, 1));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

965

MMIO_D(SKL_PS_CTRL(PIPE_B, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

966

MMIO_D(SKL_PS_CTRL(PIPE_B, 1));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

973

MMIO_D(PLANE_BUF_CFG(PIPE_B, 0));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

974

MMIO_D(PLANE_BUF_CFG(PIPE_B, 1));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

975

MMIO_D(PLANE_BUF_CFG(PIPE_B, 2));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

976

MMIO_D(PLANE_BUF_CFG(PIPE_B, 3));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

982

MMIO_D(CUR_BUF_CFG(PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

987

MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

988

MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

989

MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

994

MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

999

MMIO_D(PLANE_WM_TRANS(PIPE_B, 0));