drivers/gpu/drm/i915/display/intel_crt.c

775

while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive)

drivers/gpu/drm/i915/display/intel_crt.c

777

while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample)

drivers/gpu/drm/i915/display/intel_crt.c

790

} while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl));

drivers/gpu/drm/i915/display/intel_hdmi.c

1523

PIPEDSL(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_vblank.c

260

position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;

drivers/gpu/drm/i915/display/intel_vblank.c

280

PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;

drivers/gpu/drm/i915/display/intel_vblank.c

485

i915_reg_t reg = PIPEDSL(display, pipe);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

139

MMIO_D(PIPEDSL(display, PIPE_A));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

140

MMIO_D(PIPEDSL(display, PIPE_B));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

141

MMIO_D(PIPEDSL(display, PIPE_C));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

142

MMIO_D(PIPEDSL(display, _PIPE_EDP));