drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

633

tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

638

if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h

247

SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h

248

SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h

275

SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h

276

SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)

drivers/gpu/drm/radeon/cik.c

8855

WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,

drivers/gpu/drm/radeon/cik.c

8858

if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &

drivers/gpu/drm/radeon/evergreen.c

1874

WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,

drivers/gpu/drm/radeon/evergreen.c

1877

if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &

drivers/gpu/drm/radeon/si.c

1983

WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,

drivers/gpu/drm/radeon/si.c

1986

if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &