PHASE
DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
clock_hz = REG_READ(PHASE[inst]);
phase_hz = REG_READ(PHASE[inst]);
REG_WRITE(PHASE[inst], pixel_clk);
REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
SRII(PHASE, DP_DTO, 0),\
SRII(PHASE, DP_DTO, 1),\
SRII(PHASE, DP_DTO, 2),\
SRII(PHASE, DP_DTO, 3),\
SRII(PHASE, DP_DTO, 0),\
SRII(PHASE, DP_DTO, 1),\
SRII(PHASE, DP_DTO, 2),\
SRII(PHASE, DP_DTO, 3),\
SRII(PHASE, DP_DTO, 0),\
SRII(PHASE, DP_DTO, 1),\
SRII(PHASE, DP_DTO, 2),\
SRII(PHASE, DP_DTO, 3),\
SRII(PHASE, DP_DTO, 4),\
SRII(PHASE, DP_DTO, 0),\
SRII(PHASE, DP_DTO, 1),\
SRII(PHASE, DP_DTO, 0),\
SRII(PHASE, DP_DTO, 1),\
SRII(PHASE, DP_DTO, 2),\
SRII(PHASE, DP_DTO, 3),\
uint32_t PHASE[MAX_PIPES];
SRII(PHASE, DP_DTO, 0),\
SRII(PHASE, DP_DTO, 1),\
SRII(PHASE, DP_DTO, 2),\
SRII(PHASE, DP_DTO, 3),\
SRII(PHASE, DP_DTO, 4),\
SRII(PHASE, DP_DTO, 5),\
SRII(PHASE, DP_DTO, 0),\
SRII(PHASE, DP_DTO, 1),\
SRII(PHASE, DP_DTO, 0),\
SRII(PHASE, DP_DTO, 1),\
SRII(PHASE, DP_DTO, 2),\
SRII(PHASE, DP_DTO, 3),\
DCCG_SRII(PHASE, DTBCLK_DTO, 0), DCCG_SRII(PHASE, DTBCLK_DTO, 1), \
DCCG_SRII(PHASE, DTBCLK_DTO, 2), DCCG_SRII(PHASE, DTBCLK_DTO, 3), \
SRII_ARR_2(PHASE, DP_DTO, 0, index), \
SRII_ARR_2(PHASE, DP_DTO, 1, index), \
SRII_ARR_2(PHASE, DP_DTO, 2, index), \
SRII_ARR_2(PHASE, DP_DTO, 3, index), \
DCCG_SRII(PHASE, DP_DTO, 0), DCCG_SRII(PHASE, DP_DTO, 1), \
DCCG_SRII(PHASE, DP_DTO, 2), DCCG_SRII(PHASE, DP_DTO, 3), \
DCCG_SRII(PHASE, DP_DTO, 0), \
DCCG_SRII(PHASE, DP_DTO, 1), \
DCCG_SRII(PHASE, DP_DTO, 2), \
DCCG_SRII(PHASE, DP_DTO, 3), \
SRII_ARR_2(PHASE, DP_DTO, 0, index), \
SRII_ARR_2(PHASE, DP_DTO, 1, index), \
SRII_ARR_2(PHASE, DP_DTO, 2, index), \
SRII_ARR_2(PHASE, DP_DTO, 3, index), \
DCCG_SRII(PHASE, DP_DTO, 0), \
DCCG_SRII(PHASE, DP_DTO, 1), \
DCCG_SRII(PHASE, DP_DTO, 2), \
SRII_ARR_2(PHASE, DP_DTO, 0, index), \
SRII_ARR_2(PHASE, DP_DTO, 1, index), \
SRII_ARR_2(PHASE, DP_DTO, 2, index), \
NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, PHASE, 0));
NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, PHASE, 0));
NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, PHASE, 0));
NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, PHASE, 0));
NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, PHASE, 0));
&& !((RDW_HARPOON((ioport + hp_intstat)) & PHASE)
(PROG_HLT | RSEL | PHASE | BUS_FREE));
(PHASE | IUNKWN | PROG_HLT));
(PROG_HLT | TIMEOUT | SEL | BUS_FREE | PHASE |
WRW_HARPOON((port + hp_intstat), PHASE);
WRW_HARPOON((port + hp_intstat), PHASE);
(PHASE | RESET))
while (!(RDW_HARPOON((port + hp_intstat)) & (PHASE | RESET)) &&
WRW_HARPOON((port + hp_intstat), PHASE);
WRW_HARPOON((port + hp_intstat), PHASE);
(BUS_FREE | PHASE | XFER_CNT_0));
(BUS_FREE | PHASE))) {
WRW_HARPOON((port + hp_intstat), (BUS_FREE | PHASE | XFER_CNT_0));
while (!(RDW_HARPOON((port + hp_intstat)) & (BUS_FREE | PHASE))) {
(RESET | TIMEOUT | SEL | BUS_FREE | PHASE));