Symbol: PG_MPCC
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
1088
if (j == PG_MPCC && new_pipe->plane_res.dpp)
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
993
update_state->pg_pipe_res_update[PG_MPCC][pipe_ctx->plane_res.mpcc_inst] = false;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1012
update_state->pg_pipe_res_update[PG_MPCC][pipe_ctx->plane_res.mpcc_inst] = false;
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1135
if (j == PG_MPCC && new_pipe->plane_res.dpp)
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1290
if (!update_state->pg_pipe_res_update[PG_MPCC][i] ||
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
1366
if (update_state->pg_pipe_res_update[PG_MPCC][i] ||
drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
354
pg_cntl->pg_pipe_res_enable[PG_MPCC][mpcc_inst] = power_on;
drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
410
if (pg_cntl->pg_pipe_res_enable[PG_MPCC][i])
drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
435
pg_cntl->pg_pipe_res_enable[PG_MPCC][i] = power_on;
drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
488
pg_cntl->pg_pipe_res_enable[PG_MPCC][i] = block_enabled;
drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c
374
pg_cntl->pg_pipe_res_enable[PG_MPCC][mpcc_inst] = power_on;
drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c
538
if (pg_cntl->pg_pipe_res_enable[PG_MPCC][i])
drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c
563
pg_cntl->pg_pipe_res_enable[PG_MPCC][i] = power_on;
drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c
600
pg_cntl->pg_pipe_res_enable[PG_MPCC][i] = block_enabled;