arch/mips/sni/rm200.c

167

writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);

arch/mips/sni/rm200.c

169

writeb(cached_master_mask, rm200_pic_master + PIC_IMR);

arch/mips/sni/rm200.c

182

writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);

arch/mips/sni/rm200.c

184

writeb(cached_master_mask, rm200_pic_master + PIC_IMR);

arch/mips/sni/rm200.c

239

readb(rm200_pic_slave + PIC_IMR);

arch/mips/sni/rm200.c

240

writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);

arch/mips/sni/rm200.c

244

readb(rm200_pic_master + PIC_IMR);

arch/mips/sni/rm200.c

245

writeb(cached_master_mask, rm200_pic_master + PIC_IMR);

arch/mips/sni/rm200.c

337

writeb(0xff, rm200_pic_master + PIC_IMR);

arch/mips/sni/rm200.c

338

writeb(0xff, rm200_pic_slave + PIC_IMR);

arch/mips/sni/rm200.c

341

writeb(0, rm200_pic_master + PIC_IMR);

arch/mips/sni/rm200.c

342

writeb(1U << PIC_CASCADE_IR, rm200_pic_master + PIC_IMR);

arch/mips/sni/rm200.c

343

writeb(MASTER_ICW4_DEFAULT, rm200_pic_master + PIC_IMR);

arch/mips/sni/rm200.c

345

writeb(8, rm200_pic_slave + PIC_IMR);

arch/mips/sni/rm200.c

346

writeb(PIC_CASCADE_IR, rm200_pic_slave + PIC_IMR);

arch/mips/sni/rm200.c

347

writeb(SLAVE_ICW4_DEFAULT, rm200_pic_slave + PIC_IMR);

arch/mips/sni/rm200.c

350

writeb(cached_master_mask, rm200_pic_master + PIC_IMR);

arch/mips/sni/rm200.c

351

writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);