arch/mips/sni/rm200.c

139

#define PIC_ISR PIC_CMD

arch/mips/sni/rm200.c

194

writeb(0x0B, rm200_pic_master + PIC_CMD);

arch/mips/sni/rm200.c

195

value = readb(rm200_pic_master + PIC_CMD) & irqmask;

arch/mips/sni/rm200.c

196

writeb(0x0A, rm200_pic_master + PIC_CMD);

arch/mips/sni/rm200.c

199

writeb(0x0B, rm200_pic_slave + PIC_CMD); /* ISR register */

arch/mips/sni/rm200.c

200

value = readb(rm200_pic_slave + PIC_CMD) & (irqmask >> 8);

arch/mips/sni/rm200.c

201

writeb(0x0A, rm200_pic_slave + PIC_CMD);

arch/mips/sni/rm200.c

241

writeb(0x60+(irq & 7), rm200_pic_slave + PIC_CMD);

arch/mips/sni/rm200.c

242

writeb(0x60+PIC_CASCADE_IR, rm200_pic_master + PIC_CMD);

arch/mips/sni/rm200.c

246

writeb(0x60+irq, rm200_pic_master + PIC_CMD);

arch/mips/sni/rm200.c

302

writeb(0x0C, rm200_pic_master + PIC_CMD); /* prepare for poll */

arch/mips/sni/rm200.c

303

irq = readb(rm200_pic_master + PIC_CMD) & 7;

arch/mips/sni/rm200.c

309

writeb(0x0C, rm200_pic_slave + PIC_CMD); /* prepare for poll */

arch/mips/sni/rm200.c

310

irq = (readb(rm200_pic_slave + PIC_CMD) & 7) + 8;

arch/mips/sni/rm200.c

340

writeb(0x11, rm200_pic_master + PIC_CMD);

arch/mips/sni/rm200.c

344

writeb(0x11, rm200_pic_slave + PIC_CMD);