arch/mips/pic32/pic32mzda/early_console.c

61

uart_base + PIC32_SET(U_STA(port)));

drivers/clk/microchip/clk-core.c

107

writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg));

drivers/clk/microchip/clk-core.c

259

writel(REFO_ON | REFO_OE, PIC32_SET(refo->ctrl_reg));

drivers/clk/microchip/clk-core.c

519

writel(REFO_ON | REFO_DIVSW_EN, PIC32_SET(refo->ctrl_reg));

drivers/clk/microchip/clk-core.c

849

writel(OSC_SWEN, PIC32_SET(sclk->mux_reg));

drivers/clk/microchip/clk-core.c

961

writel(sosc->enable_mask, PIC32_SET(sosc->enable_reg));

drivers/irqchip/irq-pic32-evic.c

115

evic_base + PIC32_SET(REG_IPC_OFFSET + reg * 0x10));

drivers/irqchip/irq-pic32-evic.c

64

writel(BIT(bit), evic_base + PIC32_SET(REG_INTCON));

drivers/pinctrl/pinctrl-pic32.c

1818

writel(mask, bank->reg_base + PIC32_SET(TRIS_REG));

drivers/pinctrl/pinctrl-pic32.c

1837

writel(mask, bank->reg_base + PIC32_SET(PORT_REG));

drivers/pinctrl/pinctrl-pic32.c

1941

writel(mask, bank->reg_base +PIC32_SET(CNPU_REG));

drivers/pinctrl/pinctrl-pic32.c

1945

writel(mask, bank->reg_base + PIC32_SET(CNPD_REG));

drivers/pinctrl/pinctrl-pic32.c

1953

writel(mask, bank->reg_base + PIC32_SET(ANSEL_REG));

drivers/pinctrl/pinctrl-pic32.c

1957

writel(mask, bank->reg_base + PIC32_SET(ODCU_REG));

drivers/pinctrl/pinctrl-pic32.c

2020

writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_SET(CNCON_REG));

drivers/pinctrl/pinctrl-pic32.c

2041

writel(mask, bank->reg_base + PIC32_SET(CNEN_REG));

drivers/pinctrl/pinctrl-pic32.c

2045

writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG));

drivers/pinctrl/pinctrl-pic32.c

2051

writel(mask, bank->reg_base + PIC32_SET(CNNE_REG));

drivers/pinctrl/pinctrl-pic32.c

2053

writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG));

drivers/pinctrl/pinctrl-pic32.c

2057

writel(mask, bank->reg_base + PIC32_SET(CNEN_REG));

drivers/pinctrl/pinctrl-pic32.c

2059

writel(mask, bank->reg_base + PIC32_SET(CNNE_REG));

drivers/pinctrl/pinctrl-pic32.c

2061

writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG));

drivers/rtc/rtc-pic32.c

105

base + (enabled ? PIC32_SET(PIC32_RTCALRM) :

drivers/rtc/rtc-pic32.c

123

writel(freq << 8, base + PIC32_SET(PIC32_RTCALRM));

drivers/rtc/rtc-pic32.c

124

writel(PIC32_RTCALRM_CHIME, base + PIC32_SET(PIC32_RTCALRM));

drivers/rtc/rtc-pic32.c

277

writel(PIC32_RTCCON_RTCWREN, base + PIC32_SET(PIC32_RTCCON));

drivers/rtc/rtc-pic32.c

281

writel(PIC32_RTCCON_ON, base + PIC32_SET(PIC32_RTCCON));

drivers/tty/serial/pic32_uart.c

151

pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),

drivers/tty/serial/pic32_uart.c

222

pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),

drivers/tty/serial/pic32_uart.c

248

pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),

drivers/tty/serial/pic32_uart.c

430

pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),

drivers/tty/serial/pic32_uart.c

432

pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),

drivers/tty/serial/pic32_uart.c

612

pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),

drivers/tty/serial/pic32_uart.c

621

pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),

drivers/tty/serial/pic32_uart.c

626

pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),

drivers/tty/serial/pic32_uart.c

639

pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),

drivers/watchdog/pic32-dmt.c

48

writel(DMT_ON, PIC32_SET(dmt->regs + DMTCON_REG));

drivers/watchdog/pic32-wdt.c

109

writel(WDTCON_ON, PIC32_SET(wdt->regs + WDTCON_REG));