PHY_RESET
hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET | PHY_PDDQ, 0);
hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, HDMI_DISABLE | PHY_RESET |
hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET, PHY_RESET);
hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET, 0);
reg |= PHY_RESET;
reg &= ~PHY_RESET;
reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
writel(((val & ~PHY_RESET) | PHY_RESET), phy->base +
writel((val & ~PHY_RESET), phy->base + EMAC_EMAC_WRAPPER_CSR2);
set_bit(PHY_RESET, &tp->flags);
set_bit(PHY_RESET, &tp->flags);
set_bit(PHY_RESET, &tp->flags);
if (test_and_clear_bit(PHY_RESET, &tp->flags))
set_bit(PHY_RESET, &tp->flags);
set_bit(PHY_RESET, &tp->flags);
value = cdns_torrent_dp_read(regmap, PHY_RESET);
cdns_torrent_dp_write(regmap, PHY_RESET, value);
cdns_torrent_dp_write(regmap, PHY_RESET,
cdns_torrent_dp_write(regmap, PHY_RESET, value);
cdns_torrent_dp_write(regmap, PHY_RESET, value);
val = cdns_torrent_dp_read(regmap, PHY_RESET);
cdns_torrent_dp_write(regmap, PHY_RESET, val);
REG_FIELD(PHY_RESET, 8, 8);
REF_SSP_EN | PHY_RESET;
val &= ~PHY_RESET;
qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET,
PHY_RESET);
qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, 0);
gpreg_write(isys, PORT_B, PHY_RESET, 1);
gpreg_write(isys, id, PHY_RESET, 0);
gpreg_write(isys, id, PHY_RESET, 1);