PHY_REG - Linux

drivers/net/dsa/lan9303_mdio.c

27

mdio->bus->write(mdio->bus, PHY_ADDR(reg), PHY_REG(reg), val);

drivers/net/dsa/lan9303_mdio.c

45

return mdio->bus->read(mdio->bus, PHY_ADDR(reg), PHY_REG(reg));

drivers/net/ethernet/intel/e1000/e1000_hw.h

2916

PHY_REG(769, 17) /* Port General Configuration */

drivers/net/ethernet/intel/e1000/e1000_hw.h

2918

PHY_REG(769, 25) /* Rate Adapter Control Register */

drivers/net/ethernet/intel/e1000/e1000_hw.h

2921

PHY_REG(770, 16) /* KMRN FIFO's control/status register */

drivers/net/ethernet/intel/e1000/e1000_hw.h

2923

PHY_REG(770, 17) /* KMRN Power Management Control Register */

drivers/net/ethernet/intel/e1000/e1000_hw.h

2925

PHY_REG(770, 18) /* KMRN Inband Control Register */

drivers/net/ethernet/intel/e1000/e1000_hw.h

2927

PHY_REG(770, 19) /* KMRN Diagnostic register */

drivers/net/ethernet/intel/e1000/e1000_hw.h

2930

PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */

drivers/net/ethernet/intel/e1000/e1000_hw.h

2933

PHY_REG(776, 18) /* Voltage regulator control register */

drivers/net/ethernet/intel/e1000/e1000_hw.h

2938

PHY_REG(776, 19) /* IGP3 Capability Register */

drivers/net/ethernet/intel/e1000/e1000_hw.h

2963

#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18)

drivers/net/ethernet/intel/e1000e/ethtool.c

1351

e1e_rphy(hw, PHY_REG(2, 21), &phy_reg);

drivers/net/ethernet/intel/e1000e/ethtool.c

1354

e1e_wphy(hw, PHY_REG(2, 21), phy_reg);

drivers/net/ethernet/intel/e1000e/ethtool.c

1359

e1e_rphy(hw, PHY_REG(769, 16), &phy_reg);

drivers/net/ethernet/intel/e1000e/ethtool.c

1360

e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x000C);

drivers/net/ethernet/intel/e1000e/ethtool.c

1362

e1e_rphy(hw, PHY_REG(776, 16), &phy_reg);

drivers/net/ethernet/intel/e1000e/ethtool.c

1363

e1e_wphy(hw, PHY_REG(776, 16), phy_reg | 0x0040);

drivers/net/ethernet/intel/e1000e/ethtool.c

1365

e1e_rphy(hw, PHY_REG(769, 16), &phy_reg);

drivers/net/ethernet/intel/e1000e/ethtool.c

1366

e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x0040);

drivers/net/ethernet/intel/e1000e/ethtool.c

1368

e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);

drivers/net/ethernet/intel/e1000e/ethtool.c

1369

e1e_wphy(hw, PHY_REG(769, 20), phy_reg | 0x0400);

drivers/net/ethernet/intel/e1000e/ethtool.c

1384

e1e_rphy(hw, PHY_REG(0, 21), &phy_reg);

drivers/net/ethernet/intel/e1000e/ethtool.c

1385

e1e_wphy(hw, PHY_REG(0, 21), phy_reg & ~BIT(3));

drivers/net/ethernet/intel/e1000e/ethtool.c

1387

e1e_rphy(hw, PHY_REG(776, 18), &phy_reg);

drivers/net/ethernet/intel/e1000e/ethtool.c

1388

e1e_wphy(hw, PHY_REG(776, 18), phy_reg | 1);

drivers/net/ethernet/intel/e1000e/ich8lan.c

1626

PHY_REG(776, 20),

drivers/net/ethernet/intel/e1000e/ich8lan.c

1639

PHY_REG(776, 20),

drivers/net/ethernet/intel/e1000e/ich8lan.c

1651

PHY_REG(776, 20),

drivers/net/ethernet/intel/e1000e/ich8lan.c

2414

ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2420

ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2599

ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2713

e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2714

ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));

drivers/net/ethernet/intel/e1000e/ich8lan.c

2777

e1e_rphy(hw, PHY_REG(769, 23), &data);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2780

ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2783

e1e_rphy(hw, PHY_REG(769, 16), &data);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2785

ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2788

e1e_rphy(hw, PHY_REG(776, 20), &data);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2791

ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2794

ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2835

e1e_rphy(hw, PHY_REG(769, 23), &data);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2837

ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2840

e1e_rphy(hw, PHY_REG(769, 16), &data);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2842

ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2845

e1e_rphy(hw, PHY_REG(776, 20), &data);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2848

ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2851

ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);

drivers/net/ethernet/intel/e1000e/ich8lan.c

2861

return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));

drivers/net/ethernet/intel/e1000e/ich8lan.c

5179

ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),

drivers/net/ethernet/intel/e1000e/ich8lan.h

112

#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */

drivers/net/ethernet/intel/e1000e/ich8lan.h

113

#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */

drivers/net/ethernet/intel/e1000e/ich8lan.h

120

#define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)

drivers/net/ethernet/intel/e1000e/ich8lan.h

121

#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)

drivers/net/ethernet/intel/e1000e/ich8lan.h

122

#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)

drivers/net/ethernet/intel/e1000e/ich8lan.h

123

#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)

drivers/net/ethernet/intel/e1000e/ich8lan.h

124

#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)

drivers/net/ethernet/intel/e1000e/ich8lan.h

139

#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */

drivers/net/ethernet/intel/e1000e/ich8lan.h

140

#define HV_MUX_DATA_CTRL PHY_REG(776, 16)

drivers/net/ethernet/intel/e1000e/ich8lan.h

145

#define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */

drivers/net/ethernet/intel/e1000e/ich8lan.h

146

#define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)

drivers/net/ethernet/intel/e1000e/ich8lan.h

147

#define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */

drivers/net/ethernet/intel/e1000e/ich8lan.h

148

#define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)

drivers/net/ethernet/intel/e1000e/ich8lan.h

149

#define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */

drivers/net/ethernet/intel/e1000e/ich8lan.h

150

#define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)

drivers/net/ethernet/intel/e1000e/ich8lan.h

151

#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */

drivers/net/ethernet/intel/e1000e/ich8lan.h

152

#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)

drivers/net/ethernet/intel/e1000e/ich8lan.h

153

#define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision */

drivers/net/ethernet/intel/e1000e/ich8lan.h

154

#define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)

drivers/net/ethernet/intel/e1000e/ich8lan.h

155

#define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */

drivers/net/ethernet/intel/e1000e/ich8lan.h

156

#define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)

drivers/net/ethernet/intel/e1000e/ich8lan.h

157

#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */

drivers/net/ethernet/intel/e1000e/ich8lan.h

158

#define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)

drivers/net/ethernet/intel/e1000e/ich8lan.h

166

#define CV_SMB_CTRL PHY_REG(769, 23)

drivers/net/ethernet/intel/e1000e/ich8lan.h

170

#define I218_ULP_CONFIG1 PHY_REG(779, 16)

drivers/net/ethernet/intel/e1000e/ich8lan.h

184

#define HV_SMB_ADDR PHY_REG(768, 26)

drivers/net/ethernet/intel/e1000e/ich8lan.h

200

#define HV_OEM_BITS PHY_REG(768, 25)

drivers/net/ethernet/intel/e1000e/ich8lan.h

206

#define HV_KMRN_MODE_CTRL PHY_REG(769, 16)

drivers/net/ethernet/intel/e1000e/ich8lan.h

210

#define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16)

drivers/net/ethernet/intel/e1000e/ich8lan.h

215

#define HV_PM_CTRL PHY_REG(770, 17)

drivers/net/ethernet/intel/e1000e/ich8lan.h

219

#define I217_PLL_CLOCK_GATE_REG PHY_REG(772, 28)

drivers/net/ethernet/intel/e1000e/ich8lan.h

223

#define I217_PHY_TIMEOUTS_REG PHY_REG(770, 21)

drivers/net/ethernet/intel/e1000e/ich8lan.h

229

#define I217_INBAND_CTRL PHY_REG(770, 18)

drivers/net/ethernet/intel/e1000e/ich8lan.h

234

#define I217_LPI_GPIO_CTRL PHY_REG(772, 18)

drivers/net/ethernet/intel/e1000e/ich8lan.h

238

#define I82579_LPI_CTRL PHY_REG(772, 20)

drivers/net/ethernet/intel/e1000e/ich8lan.h

272

#define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28)

drivers/net/ethernet/intel/e1000e/ich8lan.h

274

#define I217_CGFREG PHY_REG(772, 29)

drivers/net/ethernet/intel/e1000e/ich8lan.h

276

#define I217_MEMPWR PHY_REG(772, 26)

drivers/net/ethernet/intel/e1000e/netdev.c

3072

e1e_rphy(hw, PHY_REG(770, 26), &phy_data);

drivers/net/ethernet/intel/e1000e/netdev.c

3075

e1e_wphy(hw, PHY_REG(770, 26), phy_data);

drivers/net/ethernet/intel/e1000e/regs.h

243

#define I82579_DFT_CTRL PHY_REG(769, 20)

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

285

{ PHY_REG(0), 0x00 },

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

287

{ PHY_REG(8), 0x4f }, { PHY_REG(9), 0x30 },

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

288

{ PHY_REG(10), 0x33 }, { PHY_REG(11), 0x65 },

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

292

{ PHY_REG(15), 0x80 }, { PHY_REG(16), 0x6c },

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

293

{ PHY_REG(17), 0xf2 }, { PHY_REG(18), 0x67 },

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

294

{ PHY_REG(19), 0x00 }, { PHY_REG(20), 0x10 },

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

296

{ PHY_REG(22), 0x30 }, { PHY_REG(23), 0x32 },

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

297

{ PHY_REG(24), 0x60 }, { PHY_REG(25), 0x8f },

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

298

{ PHY_REG(26), 0x00 }, { PHY_REG(27), 0x00 },

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

299

{ PHY_REG(28), 0x08 }, { PHY_REG(29), 0x00 },

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

300

{ PHY_REG(30), 0x00 }, { PHY_REG(31), 0x00 },

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

301

{ PHY_REG(32), 0x00 }, { PHY_REG(33), 0x80 },

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

302

{ PHY_REG(34), 0x00 }, { PHY_REG(35), 0x00 },

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

303

{ PHY_REG(36), 0x00 }, { PHY_REG(37), 0x00 },

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

304

{ PHY_REG(38), 0x00 }, { PHY_REG(39), 0x00 },

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

305

{ PHY_REG(40), 0x00 }, { PHY_REG(41), 0xe0 },

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

306

{ PHY_REG(42), 0x83 }, { PHY_REG(43), 0x0f },

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

307

{ PHY_REG(44), 0x3E }, { PHY_REG(45), 0xf8 },

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

308

{ PHY_REG(46), 0x00 }, { PHY_REG(47), 0x00 }

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

347

writeb(FIELD_PREP(REG12_CK_DIV_MASK, div), phy->regs + PHY_REG(12));

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

365

phy->regs + PHY_REG(13));

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

369

phy->regs + PHY_REG(14));

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

462

writeb(REG33_FIX_DA, phy->regs + PHY_REG(33));

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

470

writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(1) + i * 4);

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

474

cfg->pll_div_regs[2] >> 4), phy->regs + PHY_REG(21));

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

482

writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33));

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

484

ret = readb_poll_timeout(phy->regs + PHY_REG(34), val,

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

113

[GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

114

[GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

115

[GRF_DPHY_RX1_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 11),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

116

[GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 0),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

117

[GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 4),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

118

[GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 8),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

119

[GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 12),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

120

[GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 0),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

121

[GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 4),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

122

[GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 8),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

123

[GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 12),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

124

[GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 0),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

125

[GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 4),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

126

[GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 8),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

127

[GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 12),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

128

[GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON24, 4, 0),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

129

[GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 4),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

130

[GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 5),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

131

[GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 6),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

132

[GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 7),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

133

[GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3399_GRF_SOC_CON25, 8, 0),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

134

[GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 8),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

135

[GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 9),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

136

[GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 10),

drivers/phy/rockchip/phy-rockchip-dphy-rx0.c

137

[GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3399_GRF_SOC_STATUS1, 8, 0),

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

101

[GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 0),

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

102

[GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 1, 8),

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

103

[GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 4),

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

107

[GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 0),

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

108

[GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 1, 8),

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

109

[GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 4),

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

113

[GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 4, 8),

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

117

[GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3568_GRF_VI_CON0, 4, 0),

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

118

[GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3568_GRF_VI_CON0, 4, 4),

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

119

[GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3568_GRF_VI_CON0, 1, 8),

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

123

[GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3588_CSIDPHY_GRF_CON0, 4, 0),

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

124

[GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3588_CSIDPHY_GRF_CON0, 4, 4),

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

125

[GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3588_CSIDPHY_GRF_CON0, 1, 8),

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

327

u32 reg = PHY_REG(first, second) << 2;