PHY_CTRL1
regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
value = readl(imx_phy->base + PHY_CTRL1);
writel(value, imx_phy->base + PHY_CTRL1);
value = readl(imx_phy->base + PHY_CTRL1);
writel(value, imx_phy->base + PHY_CTRL1);
value = readl(imx_phy->base + PHY_CTRL1);
writel(value, imx_phy->base + PHY_CTRL1);
value = readl(imx_phy->base + PHY_CTRL1);
writel(value, imx_phy->base + PHY_CTRL1);
qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET,
qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, 0);