PHY_CTRL
LSDC_HDMI_REG(1, PHY_CTRL),
LSDC_HDMI_REG(0, PHY_CTRL),
return ccs_write(sensor, PHY_CTRL, val);
writel_relaxed(t->phy_ctrl, cdns_ctrl->reg + PHY_CTRL);
writel_relaxed(t->phy_ctrl, cdns_ctrl->reg + PHY_CTRL);
e1000_write_phy_reg(hw, PHY_CTRL, 0x8100);
e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
e1000_write_phy_reg(hw, PHY_CTRL, phy_reg);
e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
e1000_write_phy_reg(hw, PHY_CTRL, 0x9140);
e1000_write_phy_reg(hw, PHY_CTRL, 0x8140);
e1000_write_phy_reg(hw, PHY_CTRL, 0x4140);
e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
e1000_write_phy_reg(hw, PHY_CTRL, phy_reg);
e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
e1000_write_phy_reg(hw, PHY_CTRL, phy_reg);
ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
e1000_read_phy_reg(hw, PHY_CTRL, &mii_reg);
e1000_write_phy_reg(hw, PHY_CTRL, mii_reg);
e1000_read_phy_reg(hw, PHY_CTRL, &mii_reg);
e1000_write_phy_reg(hw, PHY_CTRL, mii_reg);
!e1000_read_phy_reg(hw, PHY_CTRL,
e1000_write_phy_reg(hw, PHY_CTRL,
!e1000_read_phy_reg(hw, PHY_CTRL, &phy_ctrl)) {
e1000_write_phy_reg(hw, PHY_CTRL, phy_ctrl);
case PHY_CTRL:
case PHY_CTRL:
mac_reg = er32(PHY_CTRL);
phy_ctrl = er32(PHY_CTRL);
ew32(PHY_CTRL, phy_ctrl);
ew32(PHY_CTRL, phy_ctrl);
phy_ctrl = er32(PHY_CTRL);
ew32(PHY_CTRL, phy_ctrl);
ew32(PHY_CTRL, phy_ctrl);
phy_ctrl = er32(PHY_CTRL);
ew32(PHY_CTRL, phy_ctrl);
reg = er32(PHY_CTRL);
ew32(PHY_CTRL, reg);
phy_ctrl = er32(PHY_CTRL);
ew32(PHY_CTRL, phy_ctrl);
(!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
rd_data = readl(regs + offset[PHY_CTRL]);
writel(rd_data, regs + offset[PHY_CTRL]);
bcm_usb_reg32_clrbits(regs + offset[PHY_CTRL],
bcm_usb_reg32_setbits(regs + offset[PHY_CTRL],
[PHY_CTRL] = 0x14,
[PHY_CTRL] = 0x10,
[PHY_CTRL] = 0xc,
regmap_write(priv->lvds_regmap, PHY_CTRL,
regmap_update_bits(priv->lvds_regmap, PHY_CTRL, LVDS_EN, LVDS_EN);
regmap_update_bits(priv->lvds_regmap, PHY_CTRL, LVDS_EN, 0);
regmap_update_bits(priv->regmap, PHY_CTRL, M_MASK | NB, val);
regmap_write(priv->regmap, PHY_CTRL + REG_SET, val);
regmap_write(priv->regmap, PHY_CTRL + REG_CLR,
regmap_write(priv->regmap, PHY_CTRL + REG_CLR,
regmap_write(priv->regmap, PHY_CTRL, CTRL_RESET_VAL);
regmap_write(priv->regmap, PHY_CTRL + REG_SET, PD);
regmap_update_bits(priv->regmap, PHY_CTRL,
PHY_CTRL, CTRL_INIT_MASK, CTRL_INIT_VAL);
rcar_gen3_phy_pcie_modify_reg(p, PHY_CTRL, PHY_CTRL_PHY_PWDN, 0);
rcar_gen3_phy_pcie_modify_reg(p, PHY_CTRL, 0, PHY_CTRL_PHY_PWDN);
u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL);
hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, phy_ctrl);
hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
HISI_SAS_DEBUGFS_REG(PHY_CTRL),