PHY_CONFIG
hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET | PHY_PDDQ, 0);
hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, HDMI_DISABLE | PHY_RESET |
hdmirx_update_bits(hdmirx_dev, PHY_CONFIG,
hdmirx_update_bits(hdmirx_dev, PHY_CONFIG,
hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, REFFREQ_SEL_MASK, REFFREQ_SEL(0));
hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, RXDATA_WIDTH, RXDATA_WIDTH);
hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET, PHY_RESET);
hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_RESET, 0);
hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, PHY_PDDQ, 0);
hdmirx_update_bits(hdmirx_dev, PHY_CONFIG, HDMI_DISABLE, 0);
et131x_mii_read(adapter, PHY_CONFIG, &tmp);
et131x_mii_read(adapter, PHY_CONFIG, ®);
PHY_CONFIG, reg);